Energy Model of Networks-on-Chip and a Bus

P.T. Wolkotte, G.J.M. Smit, N.K. Kavaldjiev, J.E. Becker, J. Becker

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    Abstract

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.
    Original languageEnglish
    Title of host publicationProceedings of the International Symposium on System-on-Chip (SoC 2005)
    EditorsJ. Nurmi, J. Takala, T.D. Hamalainen
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE
    Pages82-85
    Number of pages4
    ISBN (Print)0-7803-9294-9
    DOIs
    Publication statusPublished - Nov 2005
    EventInternational Symposium on System-on-Chip, SoC 2005 - Tampere, Finland
    Duration: 14 Nov 200517 Nov 2005

    Conference

    ConferenceInternational Symposium on System-on-Chip, SoC 2005
    Abbreviated titleSoC
    Country/TerritoryFinland
    CityTampere
    Period14/11/0517/11/05

    Keywords

    • CAES-EEA: Efficient Embedded Architectures
    • EC Grant Agreement nr.: FP6/001908
    • 2023 OA procedure

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