A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.
|Publisher||IEEE Computer Society|
|Conference||International Symposium on System-on-Chip, SoC 2005|
|Period||14/11/05 → 17/11/05|
|Other||14-17 November 2005|
- CAES-EEA: Efficient Embedded Architectures
- EC Grant Agreement nr.: FP6/001908