Energy Model of Networks-on-Chip and a Bus

P.T. Wolkotte; G.J.M. Smit; N.K. Kavaldjiev; J.E. Becker; J. Becker

doi:10.1109/ISSOC.2005.1595650

Energy Model of Networks-on-Chip and a Bus

P.T. Wolkotte, G.J.M. Smit, N.K. Kavaldjiev, J.E. Becker, J. Becker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

Original language	English
Title of host publication	Proceedings of the International Symposium on System-on-Chip (SoC 2005)
Editors	J. Nurmi, J. Takala, T.D. Hamalainen
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	82-85
Number of pages	4
ISBN (Print)	0-7803-9294-9
DOIs	https://doi.org/10.1109/ISSOC.2005.1595650
Publication status	Published - Nov 2005
Event	International Symposium on System-on-Chip, SoC 2005 - Tampere, Finland Duration: 14 Nov 2005 → 17 Nov 2005

Conference

Conference	International Symposium on System-on-Chip, SoC 2005
Abbreviated title	SoC
Country/Territory	Finland
City	Tampere
Period	14/11/05 → 17/11/05

Keywords

CAES-EEA: Efficient Embedded Architectures
EC Grant Agreement nr.: FP6/001908
2023 OA procedure

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10.1109/ISSOC.2005.1595650

ArticleFinal published version, 285 KBLicence: Taverne

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Energy Model of Networks-on-Chip and a Bus
Wolkotte, P. T., Smit, G. J. M., Kavaldjiev, N. K., Becker, J. E. & Becker, J., Jun 2005, Enschede: Centre for Telematics and Information Technology (CTIT). 5 p. (CTIT Technical Report Series; no. 05-24)
Research output: Book/Report › Report › Professional

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@inproceedings{62899e4aa8db479ca17776c0ab78dea4,

title = "Energy Model of Networks-on-Chip and a Bus",

abstract = "A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.",

keywords = "CAES-EEA: Efficient Embedded Architectures, EC Grant Agreement nr.: FP6/001908, 2023 OA procedure",

author = "P.T. Wolkotte and G.J.M. Smit and N.K. Kavaldjiev and J.E. Becker and J. Becker",

year = "2005",

month = nov,

doi = "10.1109/ISSOC.2005.1595650",

language = "English",

isbn = "0-7803-9294-9",

pages = "82--85",

editor = "J. Nurmi and J. Takala and T.D. Hamalainen",

booktitle = "Proceedings of the International Symposium on System-on-Chip (SoC 2005)",

publisher = "IEEE",

address = "United States",

note = "International Symposium on System-on-Chip, SoC 2005, SoC ; Conference date: 14-11-2005 Through 17-11-2005",

}

Wolkotte, PT, Smit, GJM, Kavaldjiev, NK, Becker, JE & Becker, J 2005, Energy Model of Networks-on-Chip and a Bus. in J Nurmi, J Takala & TD Hamalainen (eds), Proceedings of the International Symposium on System-on-Chip (SoC 2005). IEEE, Piscataway, NJ, USA, pp. 82-85, International Symposium on System-on-Chip, SoC 2005, Tampere, Finland, 14/11/05. https://doi.org/10.1109/ISSOC.2005.1595650

Energy Model of Networks-on-Chip and a Bus. / Wolkotte, P.T.; Smit, G.J.M.; Kavaldjiev, N.K. et al.
Proceedings of the International Symposium on System-on-Chip (SoC 2005). ed. / J. Nurmi; J. Takala; T.D. Hamalainen. Piscataway, NJ, USA: IEEE, 2005. p. 82-85.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Energy Model of Networks-on-Chip and a Bus

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AU - Smit, G.J.M.

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AU - Becker, J.E.

AU - Becker, J.

PY - 2005/11

Y1 - 2005/11

N2 - A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

AB - A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

KW - CAES-EEA: Efficient Embedded Architectures

KW - EC Grant Agreement nr.: FP6/001908

KW - 2023 OA procedure

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M3 - Conference contribution

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BT - Proceedings of the International Symposium on System-on-Chip (SoC 2005)

A2 - Nurmi, J.

A2 - Takala, J.

A2 - Hamalainen, T.D.

PB - IEEE

CY - Piscataway, NJ, USA

T2 - International Symposium on System-on-Chip, SoC 2005

Y2 - 14 November 2005 through 17 November 2005

ER -

Energy Model of Networks-on-Chip and a Bus

Abstract

Conference

Keywords

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Energy Model of Networks-on-Chip and a Bus

Cite this