TY - JOUR
T1 - Enhanced-Selectivity high-linearity low-noise mixer-first receiver with complex pole pair due to capacitive positive feedback
AU - Lien, Yuan-Ching
AU - Klumperink, Eric A.M.
AU - Tenbroek, Bernard
AU - Strange, Jon
AU - Nauta, Bram
PY - 2018/5/1
Y1 - 2018/5/1
N2 - A mixer-first receiver with enhanced selectivity and high dynamic range is proposed, targeting to remove SAW-filters in mobile phones and cover all frequency bands up to 6 GHz. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off and reduced distortion. This paper explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45nm Partially Depleted SOI technology achieves high out-of-band linearity (IIP3=39 dBm, IIP2=88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz.
AB - A mixer-first receiver with enhanced selectivity and high dynamic range is proposed, targeting to remove SAW-filters in mobile phones and cover all frequency bands up to 6 GHz. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off and reduced distortion. This paper explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45nm Partially Depleted SOI technology achieves high out-of-band linearity (IIP3=39 dBm, IIP2=88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz.
U2 - 10.1109/JSSC.2018.2791490
DO - 10.1109/JSSC.2018.2791490
M3 - Article
SN - 0018-9200
VL - 53
SP - 1348
EP - 1360
JO - IEEE journal of solid-state circuits
JF - IEEE journal of solid-state circuits
IS - 5
ER -