Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

S. Kan, M. Ottavi, J. Dworak

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)

Abstract

This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.
Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
DOIs
Publication statusPublished - 2015
Externally publishedYes
EventIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2015 - Amherst, United States
Duration: 12 Oct 201514 Oct 2015

Conference

ConferenceIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2015
Abbreviated titleDFT 2015
Country/TerritoryUnited States
CityAmherst
Period12/10/1514/10/15

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