Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

Senwen Kan; Marco Ottavi; Jennifer Dworak

doi:10.1109/DFT.2015.7315147

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

Senwen Kan, Marco Ottavi, Jennifer Dworak

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

Abstract

This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.

Original language	English
Title of host publication	Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	4
ISBN (Electronic)	978-1-4799-8606-4
ISBN (Print)	978-1-5090-0312-9 (USB)
DOIs	https://doi.org/10.1109/DFT.2015.7315147
Publication status	Published - 2015
Externally published	Yes
Event	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2015 - Amherst, United States Duration: 12 Oct 2015 → 14 Oct 2015

Publication series

Name	Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
Publisher	IEEE
Volume	2015
ISSN (Print)	1550-5774
ISSN (Electronic)	2377-7966

Conference

Conference	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2015
Abbreviated title	DFT 2015
Country/Territory	United States
City	Amherst
Period	12/10/15 → 14/10/15

Keywords

n/a OA procedure

Access to Document

10.1109/DFT.2015.7315147

Cite this

Kan, S., Ottavi, M., & Dworak, J. (2015). Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS); Vol. 2015). IEEE. https://doi.org/10.1109/DFT.2015.7315147

Kan, Senwen ; Ottavi, Marco ; Dworak, Jennifer. / Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). Piscataway, NJ : IEEE, 2015. (Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)).

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abstract = "This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.",

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Kan, S, Ottavi, M & Dworak, J 2015, Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. in Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), vol. 2015, IEEE, Piscataway, NJ, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2015, Amherst, Massachusetts, United States, 12/10/15. https://doi.org/10.1109/DFT.2015.7315147

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. / Kan, Senwen; Ottavi, Marco; Dworak, Jennifer.
Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). Piscataway, NJ: IEEE, 2015. (Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS); Vol. 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

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N2 - This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.

AB - This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method.

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DO - 10.1109/DFT.2015.7315147

M3 - Conference contribution

SN - 978-1-5090-0312-9 (USB)

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BT - Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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Kan S, Ottavi M, Dworak J. Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation. In Proceedings 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). Piscataway, NJ: IEEE. 2015. (Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)). doi: 10.1109/DFT.2015.7315147

Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

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Keywords

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