Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments

Jerrin  Pathrose Vareed; Ghazanfar  Ali; Hans G. Kerkhoff

doi:10.1109/APCCAS.2018.8605571

Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments

Jerrin Pathrose Vareed, Ghazanfar Ali, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper proposes a methodology to improve the robustness of CMOS physical unclonable functions with regard to environmental parameter variations and thus enhancing the security. The methodology exploits the reuse of embedded instruments which are being deployed for dependability purposes. The approach is hardware and power efficient which is especially important for applications such as IoT. Chip implementation of the embedded instruments in 40nm CMOS technology is presented in addition to simulations and experimental validation on an FPGA.

Original language	English
Title of host publication	2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Publisher	IEEE
Pages	370-373
Number of pages	4
ISBN (Electronic)	978-1-5386-8240-1
ISBN (Print)	978-1-5386-8241-8
DOIs	https://doi.org/10.1109/APCCAS.2018.8605571
Publication status	Published - 10 Jan 2019
Event	2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Shangri-La Hotel, Chengdu, China Duration: 26 Oct 2018 → 30 Oct 2018 Conference number: 14 http://apccas.com/

Conference

Conference	2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Abbreviated title	APCCAS
Country/Territory	China
City	Chengdu
Period	26/10/18 → 30/10/18
Internet address	http://apccas.com/

Keywords

Embedded Instruments
Physical unclonable function
Reliability
Temperature
IJTAG

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10.1109/APCCAS.2018.8605571

Cite this

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title = "Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments",

abstract = "This paper proposes a methodology to improve the robustness of CMOS physical unclonable functions with regard to environmental parameter variations and thus enhancing the security. The methodology exploits the reuse of embedded instruments which are being deployed for dependability purposes. The approach is hardware and power efficient which is especially important for applications such as IoT. Chip implementation of the embedded instruments in 40nm CMOS technology is presented in addition to simulations and experimental validation on an FPGA.",

keywords = "Embedded Instruments, Physical unclonable function, Reliability, Temperature, IJTAG",

author = "{Pathrose Vareed}, Jerrin and Ghazanfar Ali and Kerkhoff, {Hans G.}",

year = "2019",

month = jan,

day = "10",

doi = "10.1109/APCCAS.2018.8605571",

language = "English",

isbn = "978-1-5386-8241-8",

pages = "370--373",

booktitle = "2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)",

publisher = "IEEE",

address = "United States",

note = "2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, APCCAS ; Conference date: 26-10-2018 Through 30-10-2018",

url = "http://apccas.com/",

}

Pathrose Vareed, J, Ali, G & Kerkhoff, HG 2019, Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments. in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)., 8605571, IEEE, pp. 370-373, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 26/10/18. https://doi.org/10.1109/APCCAS.2018.8605571

TY - GEN

T1 - Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments

AU - Pathrose Vareed, Jerrin

AU - Ali, Ghazanfar

AU - Kerkhoff, Hans G.

N1 - Conference code: 14

PY - 2019/1/10

Y1 - 2019/1/10

N2 - This paper proposes a methodology to improve the robustness of CMOS physical unclonable functions with regard to environmental parameter variations and thus enhancing the security. The methodology exploits the reuse of embedded instruments which are being deployed for dependability purposes. The approach is hardware and power efficient which is especially important for applications such as IoT. Chip implementation of the embedded instruments in 40nm CMOS technology is presented in addition to simulations and experimental validation on an FPGA.

AB - This paper proposes a methodology to improve the robustness of CMOS physical unclonable functions with regard to environmental parameter variations and thus enhancing the security. The methodology exploits the reuse of embedded instruments which are being deployed for dependability purposes. The approach is hardware and power efficient which is especially important for applications such as IoT. Chip implementation of the embedded instruments in 40nm CMOS technology is presented in addition to simulations and experimental validation on an FPGA.

KW - Embedded Instruments

KW - Physical unclonable function

KW - Reliability

KW - Temperature

KW - IJTAG

U2 - 10.1109/APCCAS.2018.8605571

DO - 10.1109/APCCAS.2018.8605571

M3 - Conference contribution

SN - 978-1-5386-8241-8

SP - 370

EP - 373

BT - 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

PB - IEEE

T2 - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

Y2 - 26 October 2018 through 30 October 2018

ER -

Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments

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