Error detection in signed digit arithmetic circuit with parity checker

G.C. Cardarilli; M. Ottavi; S. Pontarelli; M. Re; A. Salsano

doi:10.1109/DFTVS.2003.1250137

Error detection in signed digit arithmetic circuit with parity checker

G.C. Cardarilli
, M. Ottavi
, S. Pontarelli
, M. Re
, A. Salsano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

Abstract

This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of signed digit representation, allowing carry-free operations. In a carry free adder, the parity can be easily checked, allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property.

Original language	English
Title of host publication	Proceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	8
ISBN (Print)	0-7695-2042-1
DOIs	https://doi.org/10.1109/DFTVS.2003.1250137
Publication status	Published - 2003
Externally published	Yes
Event	18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003 - Boston, United States Duration: 3 Nov 2003 → 5 Nov 2003

Conference

Conference	18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003
Abbreviated title	DFT 2003
Country/Territory	United States
City	Boston
Period	3/11/03 → 5/11/03

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10.1109/DFTVS.2003.1250137

Cite this

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title = "Error detection in signed digit arithmetic circuit with parity checker",

abstract = "This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of signed digit representation, allowing carry-free operations. In a carry free adder, the parity can be easily checked, allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property.",

author = "G.C. Cardarilli and M. Ottavi and S. Pontarelli and M. Re and A. Salsano",

year = "2003",

doi = "10.1109/DFTVS.2003.1250137",

language = "English",

isbn = "0-7695-2042-1",

booktitle = "Proceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

publisher = "IEEE",

address = "United States",

note = "18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003, DFT 2003 ; Conference date: 03-11-2003 Through 05-11-2003",

}

Cardarilli, GC, Ottavi, M, Pontarelli, S, Re, M & Salsano, A 2003, Error detection in signed digit arithmetic circuit with parity checker. in Proceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE, Piscataway, NJ, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003, Boston, Massachusetts, United States, 3/11/03. https://doi.org/10.1109/DFTVS.2003.1250137

TY - GEN

T1 - Error detection in signed digit arithmetic circuit with parity checker

AU - Cardarilli, G.C.

AU - Ottavi, M.

AU - Pontarelli, S.

AU - Re, M.

AU - Salsano, A.

PY - 2003

Y1 - 2003

N2 - This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of signed digit representation, allowing carry-free operations. In a carry free adder, the parity can be easily checked, allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property.

AB - This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of signed digit representation, allowing carry-free operations. In a carry free adder, the parity can be easily checked, allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property.

UR - https://www.scopus.com/pages/publications/84971238299

U2 - 10.1109/DFTVS.2003.1250137

DO - 10.1109/DFTVS.2003.1250137

M3 - Conference contribution

SN - 0-7695-2042-1

BT - Proceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

PB - IEEE

CY - Piscataway, NJ

T2 - 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003

Y2 - 3 November 2003 through 5 November 2003

ER -

Error detection in signed digit arithmetic circuit with parity checker

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