Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware

M. Westmijze, Marco Jan Gerrit Bekooij, Gerardus Johannes Maria Smit, M. Schrijver, M. Schrijver

Research output: Contribution to conferencePaperAcademicpeer-review

2 Citations (Scopus)

Abstract

The real-time system research community has paid a lot of attention to the design of safety critical hard real-time systems for which the use of non-standard hardware and operating systems can be justi﬿ed. However, stream processing applications like medical imaging systems are often not considered safety critical enough to justify the use of hard real-time techniques that would increase the cost of these systems signi﬿cantly. Instead commercial off the shelf (COTS) hardware and OS are used, and techniques at the application level are employed to reduce the variation in the end-to-end latency of these imaging processing systems. In this paper, we study the effectiveness of a number of scheduling heuristics that are intended to reduce the latency and the jitter of stream processing applications that are executed on COTS multiprocessor systems. The proposed scheduling heuristics take the execution times of tasks into account as well as dependencies between the tasks, the data structures accessed by the tasks, and the memory hierarchy. Experiments were carried out on a quad core symmetric multiprocessing (SMP) Intel processor. These experiments show that the proposed heuristics can reduce the end-to-end latency with almost 60%, and reduce the variation in the latency with more than 90% when compared with a naive scheduling heuristic that does not consider execution times, dependencies and the memory hierarchy.
Original languageUndefined
Pages140-146
Number of pages7
DOIs
Publication statusPublished - 2011
Event9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011 - Taipei, Taiwan, Province of China
Duration: 13 Oct 201114 Oct 2011
Conference number: 9

Conference

Conference9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011
Abbreviated titleESTIMedia
CountryTaiwan, Province of China
CityTaipei
Period13/10/1114/10/11

Keywords

  • IR-81230
  • EWI-22154

Cite this

Westmijze, M., Bekooij, M. J. G., Smit, G. J. M., Schrijver, M., & Schrijver, M. (2011). Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware. 140-146. Paper presented at 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, Province of China. https://doi.org/10.1109/ESTIMedia.2011.6088520
Westmijze, M. ; Bekooij, Marco Jan Gerrit ; Smit, Gerardus Johannes Maria ; Schrijver, M. ; Schrijver, M. / Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware. Paper presented at 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, Province of China.7 p.
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title = "Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware",
abstract = "The real-time system research community has paid a lot of attention to the design of safety critical hard real-time systems for which the use of non-standard hardware and operating systems can be justi﬿ed. However, stream processing applications like medical imaging systems are often not considered safety critical enough to justify the use of hard real-time techniques that would increase the cost of these systems signi﬿cantly. Instead commercial off the shelf (COTS) hardware and OS are used, and techniques at the application level are employed to reduce the variation in the end-to-end latency of these imaging processing systems. In this paper, we study the effectiveness of a number of scheduling heuristics that are intended to reduce the latency and the jitter of stream processing applications that are executed on COTS multiprocessor systems. The proposed scheduling heuristics take the execution times of tasks into account as well as dependencies between the tasks, the data structures accessed by the tasks, and the memory hierarchy. Experiments were carried out on a quad core symmetric multiprocessing (SMP) Intel processor. These experiments show that the proposed heuristics can reduce the end-to-end latency with almost 60{\%}, and reduce the variation in the latency with more than 90{\%} when compared with a naive scheduling heuristic that does not consider execution times, dependencies and the memory hierarchy.",
keywords = "IR-81230, EWI-22154",
author = "M. Westmijze and Bekooij, {Marco Jan Gerrit} and Smit, {Gerardus Johannes Maria} and M. Schrijver and M. Schrijver",
year = "2011",
doi = "10.1109/ESTIMedia.2011.6088520",
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Westmijze, M, Bekooij, MJG, Smit, GJM, Schrijver, M & Schrijver, M 2011, 'Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware' Paper presented at 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, Province of China, 13/10/11 - 14/10/11, pp. 140-146. https://doi.org/10.1109/ESTIMedia.2011.6088520

Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware. / Westmijze, M.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria; Schrijver, M.; Schrijver, M.

2011. 140-146 Paper presented at 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, Province of China.

Research output: Contribution to conferencePaperAcademicpeer-review

TY - CONF

T1 - Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware

AU - Westmijze, M.

AU - Bekooij, Marco Jan Gerrit

AU - Smit, Gerardus Johannes Maria

AU - Schrijver, M.

AU - Schrijver, M.

PY - 2011

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N2 - The real-time system research community has paid a lot of attention to the design of safety critical hard real-time systems for which the use of non-standard hardware and operating systems can be justi﬿ed. However, stream processing applications like medical imaging systems are often not considered safety critical enough to justify the use of hard real-time techniques that would increase the cost of these systems signi﬿cantly. Instead commercial off the shelf (COTS) hardware and OS are used, and techniques at the application level are employed to reduce the variation in the end-to-end latency of these imaging processing systems. In this paper, we study the effectiveness of a number of scheduling heuristics that are intended to reduce the latency and the jitter of stream processing applications that are executed on COTS multiprocessor systems. The proposed scheduling heuristics take the execution times of tasks into account as well as dependencies between the tasks, the data structures accessed by the tasks, and the memory hierarchy. Experiments were carried out on a quad core symmetric multiprocessing (SMP) Intel processor. These experiments show that the proposed heuristics can reduce the end-to-end latency with almost 60%, and reduce the variation in the latency with more than 90% when compared with a naive scheduling heuristic that does not consider execution times, dependencies and the memory hierarchy.

AB - The real-time system research community has paid a lot of attention to the design of safety critical hard real-time systems for which the use of non-standard hardware and operating systems can be justi﬿ed. However, stream processing applications like medical imaging systems are often not considered safety critical enough to justify the use of hard real-time techniques that would increase the cost of these systems signi﬿cantly. Instead commercial off the shelf (COTS) hardware and OS are used, and techniques at the application level are employed to reduce the variation in the end-to-end latency of these imaging processing systems. In this paper, we study the effectiveness of a number of scheduling heuristics that are intended to reduce the latency and the jitter of stream processing applications that are executed on COTS multiprocessor systems. The proposed scheduling heuristics take the execution times of tasks into account as well as dependencies between the tasks, the data structures accessed by the tasks, and the memory hierarchy. Experiments were carried out on a quad core symmetric multiprocessing (SMP) Intel processor. These experiments show that the proposed heuristics can reduce the end-to-end latency with almost 60%, and reduce the variation in the latency with more than 90% when compared with a naive scheduling heuristic that does not consider execution times, dependencies and the memory hierarchy.

KW - IR-81230

KW - EWI-22154

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M3 - Paper

SP - 140

EP - 146

ER -

Westmijze M, Bekooij MJG, Smit GJM, Schrijver M, Schrijver M. Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware. 2011. Paper presented at 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, Province of China. https://doi.org/10.1109/ESTIMedia.2011.6088520