Experience with a clustered parallel reduction machine

M. Beemster, P.H. Hartel, L.O. Hertzberger, R.F.H. Hofman, K.G. Langendoen, L.L. Li, R. Milikowski, W.G. Vree, H.P. Barendregt, J.C. Mulder

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    Abstract

    A clustered architecture has been designed to exploit divide and conquer parallelism in functional programs. The programming methodology developed for the machine is based on explicit annotations and program transformations. It has been successfully applied to a number of algorithms resulting in a benchmark of small andmediumsize parallel functional programs. Sophisticated compilation techniques are used such as strictness analysis on non-flat domains and RISC and VLIW code generation. Parallel jobs are distributed by an efficient hierarchical scheduler. A special processor for graph reduction has been designed as a basic building block for the machine. A prototype of a single cluster machine has been constructed with stock hardware. This paper describes the experience with the project and its current state.
    Original languageEnglish
    Pages (from-to)175-200
    Number of pages26
    JournalFuture generation computer systems
    Volume9
    Issue number3
    DOIs
    Publication statusPublished - Sep 1993

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