Exploration within the Network-on-Chip Paradigm

Pascal T. Wolkotte

Research output: ThesisPhD Thesis - Research UT, graduation UT

182 Downloads (Pure)

Abstract

A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Due to the continuous increase of the number of transistors available on-chip and the operational clock frequency, it became impossible to reach every function within the chip in a single clock cycle. Furthermore, centralized control became hard with the increase in functionality. This lead to the current move towards integrating a set of independent processing cores into a single chip.
These multi-core architectures rely on a well designed on-chip communication architecture. Global wires and bus-based systems need to be replaced to overcome the problem of wiring and the single point of arbitration. This is introduced as the Network-on-Chip (NoC) paradigm. In this work we explore the paradigm by implementation and characterization of multiple NoC router architectures. The scope of the communication architecture is the embedding in a heterogeneous multi-core System-on-Chip for streaming applications. Based on application analysis we propose a circuit switched router architecture and improve an existing packet switched router architecture that also oers QoS.
The two routers are compared in-depth with two other packet switched router design on both latency and energy performance. Furthermore, to speed-up cycle and bit-accurate simulations, we developed a framework for large many-core architectures on a single FPGA using a sequential simulation approach.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • University of Twente
Supervisors/Advisors
  • Smit, G.J.M., Supervisor
Thesis sponsors
Award date16 Jan 2009
Place of PublicationEnschede
Publisher
Print ISBNs978-90-365-2757-6
DOIs
Publication statusPublished - 16 Jan 2009

Keywords

  • Energy
  • Network-on-chip
  • Computer architecture
  • System on chip
  • Simulation
  • CAES-EEA: Efficient Embedded Architectures
  • EC Grant Agreement nr.: FP6/001908

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