F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

S. Campitelli, M. Ottavi, S. Pontarelli, A. Marchioro, D. Felici, F. Lombardi

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

18 Citations (Scopus)

Abstract

This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013 - New York, United States
Duration: 2 Oct 20134 Oct 2013

Conference

Conference2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013
Abbreviated titleDFT
Country/TerritoryUnited States
CityNew York
Period2/10/134/10/13

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