F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

S. Campitelli; M. Ottavi; S. Pontarelli; A. Marchioro; D. Felici; F. Lombardi

doi:10.1109/DFT.2013.6653591

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

S. Campitelli
, M. Ottavi
, S. Pontarelli
, A. Marchioro
, D. Felici
, F. Lombardi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

20 Citations (Scopus)

Abstract

This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFT.2013.6653591
Publication status	Published - 2013
Externally published	Yes
Event	2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013 - New York, United States Duration: 2 Oct 2013 → 4 Oct 2013

Conference

Conference	2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013
Abbreviated title	DFT
Country/Territory	United States
City	New York
Period	2/10/13 → 4/10/13

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10.1109/DFT.2013.6653591

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title = "F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments",

abstract = "This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.",

author = "S. Campitelli and M. Ottavi and S. Pontarelli and A. Marchioro and D. Felici and F. Lombardi",

year = "2013",

doi = "10.1109/DFT.2013.6653591",

language = "English",

booktitle = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

note = "2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013, DFT ; Conference date: 02-10-2013 Through 04-10-2013",

}

Campitelli, S, Ottavi, M, Pontarelli, S, Marchioro, A, Felici, D & Lombardi, F 2013, F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013, New York, New York, United States, 2/10/13. https://doi.org/10.1109/DFT.2013.6653591

TY - GEN

T1 - F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

AU - Campitelli, S.

AU - Ottavi, M.

AU - Pontarelli, S.

AU - Marchioro, A.

AU - Felici, D.

AU - Lombardi, F.

PY - 2013

Y1 - 2013

N2 - This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.

AB - This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.

UR - https://www.scopus.com/pages/publications/84891303068

U2 - 10.1109/DFT.2013.6653591

DO - 10.1109/DFT.2013.6653591

M3 - Conference contribution

BT - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

T2 - 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013

Y2 - 2 October 2013 through 4 October 2013

ER -

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

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