Fast, Accurate and Detailed NoC Simulations

P.T. Wolkotte, P.K.F. Holzenspies, Gerardus Johannes Maria Smit

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    57 Citations (Scopus)
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    Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy.
    Original languageUndefined
    Title of host publicationProceedings of the 1st ACM/IEEE International Symposium on Networks-on-Chip
    EditorsP. Kellenberger
    Place of PublicationLos Alamitos
    PublisherIEEE Computer Society
    Number of pages10
    ISBN (Print)978-0-7695-2773-4
    Publication statusPublished - May 2007
    Event1st ACM/IEEE International Symposium on Networks-on-Chip - Princeton, NJ, USA
    Duration: 6 May 20079 May 2007

    Publication series

    PublisherIEEE Computer Society Press


    Conference1st ACM/IEEE International Symposium on Networks-on-Chip
    Other6-9 May 2007


    • EC Grant Agreement nr.: FP6/001908
    • METIS-242170
    • CAES-EEA: Efficient Embedded Architectures
    • IR-67114
    • EWI-9855

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