Fast Fault Simulation for Nonlinear Analogue Circuits

Nur Engin; Hans G. Kerkhoff

doi:10.1109/MDT.2003.1188261

Fast Fault Simulation for Nonlinear Analogue Circuits

Nur Engin
, Hans G. Kerkhoff

Research output: Contribution to journal › Article › Academic › peer-review

5 Citations (Scopus)

Abstract

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.

Original language	English
Pages (from-to)	40-47
Number of pages	8
Journal	IEEE Design & Test of Computers
Volume	20
Issue number	2
DOIs	https://doi.org/10.1109/MDT.2003.1188261
Publication status	Published - 2003

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10.1109/MDT.2003.1188261

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Fast Fault Simulation for Nonlinear Analogue Circuits

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