Cache memories are very relevant components in modern processors, and therefore, their protection against soft errors is important to ensure reliability. One important element in caches is the tag fields, which are critical to keep data integrity and achieve a high hit ratio. To protect them against soft errors, a parity bit or a single error correction (SEC) code is commonly used. In that case, on each cache access, the parity bit is checked or the SEC code decoded on each cache way to detect and correct errors. In this paper, FastTag, a novel approach to protect cache tags is presented and evaluated. The proposed scheme computes the parity or SEC bits on the incoming address and compares the result with the tag and parity bits stored in each cache way. This avoids parity recomputation or SEC decoding, thus reducing the circuit complexity. This is corroborated by the evaluation results that show how FastTag requires an area, delay, and power overhead much lower than the conventional techniques that are currently used.
|Journal||IEEE transactions on device and materials reliability|
|Publication status||Published - 2014|