FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs

Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

20 Citations (Scopus)
46 Downloads (Pure)

Abstract

During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee a certain accuracy of the results. In this paper, we propose a new technique for approximate addition optimized for LUT-Based FPGAs with segmented carry chains. Our optimized adder structure is able to a) best exploit artifacts of LUT-Based FPGAs such as unused inputs and b) provide a smaller average error than previously proposed approximate adder structures, as well as c) a reduced critical path delay than dedicated accurate logic in modern FPGAs. We present a novel stochastic error calculus that is able to take into account also non-uniform input distributions and present a detailed comparison of approximate adder structures proposed in literature with our novel LUT-Based approximate arithmetic structure.

Original languageEnglish
Title of host publication2016 International Conference on Field-Programmable Technology, FPT 2016
PublisherIEEE
Pages213-216
Number of pages4
ISBN (Electronic)978-1-5090-5602-6
ISBN (Print)978-1-5090-5603-3
DOIs
Publication statusPublished - 15 May 2017
Externally publishedYes
Event2016 International Conference on Field-Programmable Technology, FPT 2016 - Xi'an, China
Duration: 7 Dec 20169 Dec 2016
Conference number: 15

Conference

Conference2016 International Conference on Field-Programmable Technology, FPT 2016
Abbreviated titleFPT
Country/TerritoryChina
CityXi'an
Period7/12/169/12/16

Keywords

  • Approximate adder
  • Approximate computing
  • Low-latency adders
  • LUT-Based FPGAs
  • n/a OA procedure

Fingerprint

Dive into the research topics of 'FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs'. Together they form a unique fingerprint.

Cite this