TY - JOUR
T1 - Feedforward phase noise cancellation exploiting a sub-sampling phase detector
AU - Thijssen, Bartholomeus Jacobus
AU - Klumperink, Eric A.M.
AU - Quinlan, Philip
AU - Nauta, Bram
PY - 2018/11/1
Y1 - 2018/11/1
N2 - This paper presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for cancellation. Both phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A subsampling phase-locked loop with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The phase noise reduction bandwidth is increased to almost a third of the reference frequency — 3x the maximal bandwidth for 3rd order type-II PLLs. The proposed analytical model shows a phase noise reduction of 9 dB at a frequency offset of fref =10. The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.
AB - This paper presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for cancellation. Both phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A subsampling phase-locked loop with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The phase noise reduction bandwidth is increased to almost a third of the reference frequency — 3x the maximal bandwidth for 3rd order type-II PLLs. The proposed analytical model shows a phase noise reduction of 9 dB at a frequency offset of fref =10. The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.
U2 - 10.1109/TCSII.2017.2764096
DO - 10.1109/TCSII.2017.2764096
M3 - Article
SN - 1549-7747
VL - 65
SP - 1574
EP - 1578
JO - IEEE transactions on circuits and systems II: express briefs
JF - IEEE transactions on circuits and systems II: express briefs
IS - 11
ER -