Fixed latency on-chip interconnect for hardware spiking neural network architectures

Sandeep Pande, Fearghal Morgan, Gerardus Johannes Maria Smit, Tom Bruintjes, J.H. Rutgers, Seamus Cawley, Jim Harkin, Liam McDaid

    Research output: Contribution to journalArticleAcademicpeer-review

    15 Citations (Scopus)
    188 Downloads (Pure)

    Abstract

    Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructure offers scalable connectivity for spike communication in hardware SNN architectures. However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency. This packet latency jitter distorts the timing information conveyed on the synaptic connections in the SNN, resulting in unreliable application behaviour. This paper presents a SystemC simulation based analysis of the synaptic information distortion in NoC based hardware SNNs. The paper proposes a fixed spike transfer latency ring topology interconnect for spike communication between neural tiles, using a novel timestamped spike broadcast flow control scheme. The proposed architectural technique is evaluated using spike rates employed in previously reported mesh topology NoC based hardware SNN applications, which exhibited spike latency jitter over NoC paths. Results indicate that the proposed interconnect offers fixed spike transfer latency and eliminates the associated information distortion. The paper presents the micro-architecture of the proposed ring router. The FPGA validated ring interconnect architecture has been synthesised using 65nm low-power CMOS technology. Silicon area comparisons for various ring sizes are presented. Scalability of the proposed architecture has been addressed by employing a hierarchical NoC architecture.
    Original languageUndefined
    Pages (from-to)357-371
    Number of pages23
    JournalParallel computing
    Volume39
    Issue number9
    DOIs
    Publication statusPublished - Sep 2013

    Keywords

    • EWI-23312
    • Latency Jitter
    • Spiking Neural Networks (SNN)
    • IR-85838
    • Network on Chip (NoC)
    • METIS-296413
    • Synaptic Connectivity

    Cite this

    Pande, S., Morgan, F., Smit, G. J. M., Bruintjes, T., Rutgers, J. H., Cawley, S., ... McDaid, L. (2013). Fixed latency on-chip interconnect for hardware spiking neural network architectures. Parallel computing, 39(9), 357-371. https://doi.org/10.1016/j.parco.2013.04.010
    Pande, Sandeep ; Morgan, Fearghal ; Smit, Gerardus Johannes Maria ; Bruintjes, Tom ; Rutgers, J.H. ; Cawley, Seamus ; Harkin, Jim ; McDaid, Liam. / Fixed latency on-chip interconnect for hardware spiking neural network architectures. In: Parallel computing. 2013 ; Vol. 39, No. 9. pp. 357-371.
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    abstract = "Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructure offers scalable connectivity for spike communication in hardware SNN architectures. However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency. This packet latency jitter distorts the timing information conveyed on the synaptic connections in the SNN, resulting in unreliable application behaviour. This paper presents a SystemC simulation based analysis of the synaptic information distortion in NoC based hardware SNNs. The paper proposes a fixed spike transfer latency ring topology interconnect for spike communication between neural tiles, using a novel timestamped spike broadcast flow control scheme. The proposed architectural technique is evaluated using spike rates employed in previously reported mesh topology NoC based hardware SNN applications, which exhibited spike latency jitter over NoC paths. Results indicate that the proposed interconnect offers fixed spike transfer latency and eliminates the associated information distortion. The paper presents the micro-architecture of the proposed ring router. The FPGA validated ring interconnect architecture has been synthesised using 65nm low-power CMOS technology. Silicon area comparisons for various ring sizes are presented. Scalability of the proposed architecture has been addressed by employing a hierarchical NoC architecture.",
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    author = "Sandeep Pande and Fearghal Morgan and Smit, {Gerardus Johannes Maria} and Tom Bruintjes and J.H. Rutgers and Seamus Cawley and Jim Harkin and Liam McDaid",
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    Pande, S, Morgan, F, Smit, GJM, Bruintjes, T, Rutgers, JH, Cawley, S, Harkin, J & McDaid, L 2013, 'Fixed latency on-chip interconnect for hardware spiking neural network architectures', Parallel computing, vol. 39, no. 9, pp. 357-371. https://doi.org/10.1016/j.parco.2013.04.010

    Fixed latency on-chip interconnect for hardware spiking neural network architectures. / Pande, Sandeep; Morgan, Fearghal; Smit, Gerardus Johannes Maria; Bruintjes, Tom; Rutgers, J.H.; Cawley, Seamus; Harkin, Jim; McDaid, Liam.

    In: Parallel computing, Vol. 39, No. 9, 09.2013, p. 357-371.

    Research output: Contribution to journalArticleAcademicpeer-review

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    AU - Smit, Gerardus Johannes Maria

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    AU - Rutgers, J.H.

    AU - Cawley, Seamus

    AU - Harkin, Jim

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    KW - Synaptic Connectivity

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