Flip-Flops for accurate multiphase clocking: transmission gate versus current mode logic

Research output: Contribution to journalArticleAcademicpeer-review

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Abstract

Dynamic transmission gate (DTG) flip-flops (FFs) (DTG-FFs) and current mode logic (CML) FFs (CML-FFs) are compared targeting power efficient multiphase clock generation with low phase error. The effect of component mismatches on multiphase clock timing inaccuracies is modeled and compared, using the product of mismatch-induced jitter variance and power consumption as a figure-of-merit (FOM). Analytical equations are derived to estimate the jitter–power FOM for DTG-FF- and CMLFF- based dividers. Simulations confirm the trends predicted by the equations and show that DTG-FFs achieve a better FOM than CML-FFs. The advantage increases for CMOS processes with smaller feature size and for a lower input frequency compared to $f_T$.
Original languageEnglish
Pages (from-to)422-426
Number of pages5
JournalIEEE transactions on circuits and systems II: express briefs
Volume60
Issue number7
DOIs
Publication statusPublished - 27 May 2013

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Flip flop circuits
Clocks
Jitter
Electric power utilization

Keywords

  • EWI-23492
  • IR-86547
  • METIS-297722
  • Timing
  • Phase error
  • Mismatch
  • Jitter
  • Multi-Phase Clocks
  • Dynamic transmission gate logic
  • Current Mode Logic
  • Divider
  • Flip-flop design
  • Low power
  • Power efficiency

Cite this

@article{228c98ca133d40df9768c21b944b039d,
title = "Flip-Flops for accurate multiphase clocking: transmission gate versus current mode logic",
abstract = "Dynamic transmission gate (DTG) flip-flops (FFs) (DTG-FFs) and current mode logic (CML) FFs (CML-FFs) are compared targeting power efficient multiphase clock generation with low phase error. The effect of component mismatches on multiphase clock timing inaccuracies is modeled and compared, using the product of mismatch-induced jitter variance and power consumption as a figure-of-merit (FOM). Analytical equations are derived to estimate the jitter–power FOM for DTG-FF- and CMLFF- based dividers. Simulations confirm the trends predicted by the equations and show that DTG-FFs achieve a better FOM than CML-FFs. The advantage increases for CMOS processes with smaller feature size and for a lower input frequency compared to $f_T$.",
keywords = "EWI-23492, IR-86547, METIS-297722, Timing, Phase error, Mismatch, Jitter, Multi-Phase Clocks, Dynamic transmission gate logic, Current Mode Logic, Divider, Flip-flop design, Low power, Power efficiency",
author = "R. Dutta and Klumperink, {Eric A.M.} and X. Gao and Z. Ru and {van der Zee}, {Ronan A.R.} and Bram Nauta",
note = "eemcs-eprint-23492",
year = "2013",
month = "5",
day = "27",
doi = "10.1109/TCSII.2013.2261173",
language = "English",
volume = "60",
pages = "422--426",
journal = "IEEE transactions on circuits and systems II: express briefs",
issn = "1549-7747",
publisher = "IEEE",
number = "7",

}

Flip-Flops for accurate multiphase clocking : transmission gate versus current mode logic. / Dutta, R.; Klumperink, Eric A.M.; Gao, X.; Ru, Z.; van der Zee, Ronan A.R.; Nauta, Bram.

In: IEEE transactions on circuits and systems II: express briefs, Vol. 60, No. 7, 27.05.2013, p. 422-426.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - Flip-Flops for accurate multiphase clocking

T2 - transmission gate versus current mode logic

AU - Dutta, R.

AU - Klumperink, Eric A.M.

AU - Gao, X.

AU - Ru, Z.

AU - van der Zee, Ronan A.R.

AU - Nauta, Bram

N1 - eemcs-eprint-23492

PY - 2013/5/27

Y1 - 2013/5/27

N2 - Dynamic transmission gate (DTG) flip-flops (FFs) (DTG-FFs) and current mode logic (CML) FFs (CML-FFs) are compared targeting power efficient multiphase clock generation with low phase error. The effect of component mismatches on multiphase clock timing inaccuracies is modeled and compared, using the product of mismatch-induced jitter variance and power consumption as a figure-of-merit (FOM). Analytical equations are derived to estimate the jitter–power FOM for DTG-FF- and CMLFF- based dividers. Simulations confirm the trends predicted by the equations and show that DTG-FFs achieve a better FOM than CML-FFs. The advantage increases for CMOS processes with smaller feature size and for a lower input frequency compared to $f_T$.

AB - Dynamic transmission gate (DTG) flip-flops (FFs) (DTG-FFs) and current mode logic (CML) FFs (CML-FFs) are compared targeting power efficient multiphase clock generation with low phase error. The effect of component mismatches on multiphase clock timing inaccuracies is modeled and compared, using the product of mismatch-induced jitter variance and power consumption as a figure-of-merit (FOM). Analytical equations are derived to estimate the jitter–power FOM for DTG-FF- and CMLFF- based dividers. Simulations confirm the trends predicted by the equations and show that DTG-FFs achieve a better FOM than CML-FFs. The advantage increases for CMOS processes with smaller feature size and for a lower input frequency compared to $f_T$.

KW - EWI-23492

KW - IR-86547

KW - METIS-297722

KW - Timing

KW - Phase error

KW - Mismatch

KW - Jitter

KW - Multi-Phase Clocks

KW - Dynamic transmission gate logic

KW - Current Mode Logic

KW - Divider

KW - Flip-flop design

KW - Low power

KW - Power efficiency

U2 - 10.1109/TCSII.2013.2261173

DO - 10.1109/TCSII.2013.2261173

M3 - Article

VL - 60

SP - 422

EP - 426

JO - IEEE transactions on circuits and systems II: express briefs

JF - IEEE transactions on circuits and systems II: express briefs

SN - 1549-7747

IS - 7

ER -