Flip-Flops for accurate multiphase clocking: transmission gate versus current mode logic

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    Dynamic transmission gate (DTG) flip-flops (FFs) (DTG-FFs) and current mode logic (CML) FFs (CML-FFs) are compared targeting power efficient multiphase clock generation with low phase error. The effect of component mismatches on multiphase clock timing inaccuracies is modeled and compared, using the product of mismatch-induced jitter variance and power consumption as a figure-of-merit (FOM). Analytical equations are derived to estimate the jitter–power FOM for DTG-FF- and CMLFF- based dividers. Simulations confirm the trends predicted by the equations and show that DTG-FFs achieve a better FOM than CML-FFs. The advantage increases for CMOS processes with smaller feature size and for a lower input frequency compared to $f_T$.
    Original languageEnglish
    Pages (from-to)422-426
    Number of pages5
    JournalIEEE transactions on circuits and systems II: express briefs
    Issue number7
    Publication statusPublished - 27 May 2013


    • EWI-23492
    • IR-86547
    • METIS-297722
    • Timing
    • Phase error
    • Mismatch
    • Jitter
    • Multi-Phase Clocks
    • Dynamic transmission gate logic
    • Current Mode Logic
    • Divider
    • Flip-flop design
    • Low power
    • Power efficiency


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