Floorplan Optimized Topological Partitioning of Programmed Logic Arrays

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proceedings of the WG 10.5 IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design
Place of Publication	Amsterdam
Publisher	North Holland
Pages	190-200
ISBN (Print)	0444814795
Publication status	Published - 13 Mar 1992

Cite this

@inproceedings{7ab7c02fb3be4ed7a4b356e9a070b069,

title = "Floorplan Optimized Topological Partitioning of Programmed Logic Arrays",

author = "\{ten Berg\}, A.J.W.M.",

year = "1992",

month = mar,

day = "13",

language = "English",

isbn = "0444814795",

pages = "190--200",

booktitle = "Proceedings of the WG 10.5 IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design",

publisher = "North Holland",

address = "Netherlands",

}

Floorplan Optimized Topological Partitioning of Programmed Logic Arrays. / ten Berg, A.J.W.M.
Proceedings of the WG 10.5 IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design. Amsterdam: North Holland, 1992. p. 190-200.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review