Folding stage and folding analog-to-digital converter

Bram Nauta (Inventor), Arnoldus G.W. Venes (Inventor)

    Research output: Patent

    19 Downloads (Pure)

    Abstract

    A folding stage for a folding analog-to-digital converter includes a plurality of consecutive reference terminals providing ascending different reference voltages, a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs wherein each of the pairs has a first transistor having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of the consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A current-to-voltage converter includes a first resistor connected between the first output node and the first summing node to provide a first output voltage.
    Original languageUndefined
    Patent numberUS005640163A
    Priority date7/07/94
    Publication statusPublished - 17 Jun 1997

    Keywords

    • IR-102632
    • EWI-27524

    Cite this

    Nauta, B., & Venes, A. G. W. (1997). Folding stage and folding analog-to-digital converter. (Patent No. US005640163A).
    Nauta, Bram (Inventor) ; Venes, Arnoldus G.W. (Inventor). / Folding stage and folding analog-to-digital converter. Patent No.: US005640163A.
    @misc{6652bca5c67a44668f0e289921fbd260,
    title = "Folding stage and folding analog-to-digital converter",
    abstract = "A folding stage for a folding analog-to-digital converter includes a plurality of consecutive reference terminals providing ascending different reference voltages, a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs wherein each of the pairs has a first transistor having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of the consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A current-to-voltage converter includes a first resistor connected between the first output node and the first summing node to provide a first output voltage.",
    keywords = "IR-102632, EWI-27524",
    author = "Bram Nauta and Venes, {Arnoldus G.W.}",
    year = "1997",
    month = "6",
    day = "17",
    language = "Undefined",
    type = "Patent",
    note = "US005640163A",

    }

    Nauta, B & Venes, AGW 1997, Folding stage and folding analog-to-digital converter, Patent No. US005640163A.

    Folding stage and folding analog-to-digital converter. / Nauta, Bram (Inventor); Venes, Arnoldus G.W. (Inventor).

    Patent No.: US005640163A.

    Research output: Patent

    TY - PAT

    T1 - Folding stage and folding analog-to-digital converter

    AU - Nauta, Bram

    AU - Venes, Arnoldus G.W.

    PY - 1997/6/17

    Y1 - 1997/6/17

    N2 - A folding stage for a folding analog-to-digital converter includes a plurality of consecutive reference terminals providing ascending different reference voltages, a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs wherein each of the pairs has a first transistor having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of the consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A current-to-voltage converter includes a first resistor connected between the first output node and the first summing node to provide a first output voltage.

    AB - A folding stage for a folding analog-to-digital converter includes a plurality of consecutive reference terminals providing ascending different reference voltages, a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs wherein each of the pairs has a first transistor having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of the consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A current-to-voltage converter includes a first resistor connected between the first output node and the first summing node to provide a first output voltage.

    KW - IR-102632

    KW - EWI-27524

    M3 - Patent

    M1 - US005640163A

    ER -

    Nauta B, Venes AGW, inventors. Folding stage and folding analog-to-digital converter. US005640163A. 1997 Jun 17.