TY - JOUR
T1 - FPGA-based dynamically reconfigurable SQL query processing
AU - Ziener, Daniel
AU - Bauer, Florian
AU - Becher, Andreas
AU - Dennl, Christopher
AU - Meyer-Wegener, Klaus
AU - Schurfeld, Ute
AU - Teich, Jürgen
AU - Vogt, Jörg Stephan
AU - Weber, Helmut
PY - 2016/8/1
Y1 - 2016/8/1
N2 - In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row-as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.
AB - In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row-as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.
KW - Dynamic partial reconfiguration
KW - FPGA
KW - Reconfigurable computing
KW - SQL processing
UR - http://www.scopus.com/inward/record.url?scp=84984660700&partnerID=8YFLogxK
U2 - 10.1145/2845087
DO - 10.1145/2845087
M3 - Article
AN - SCOPUS:84984660700
SN - 1936-7406
VL - 9
JO - ACM Transactions on Reconfigurable Technology and Systems
JF - ACM Transactions on Reconfigurable Technology and Systems
IS - 4
M1 - 25
ER -