Frequency divider

M. Acar; Bram Nauta; Dominicus Martinus Wilhelmus Leenaerts

Frequency divider

M. Acar (Inventor), Bram Nauta (Inventor), Dominicus Martinus Wilhelmus Leenaerts (Inventor)

Research output: Patent

141 Downloads (Pure)

Abstract

A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.

Original language	Undefined
Patent number	US7671641 B1
Priority date	4/03/05
Publication status	Published - 2 Mar 2010

Keywords

IR-102633
METIS-237874
EWI-8932

Access to Document

https://worldwide.espacenet.com/publicationDetails/originalDocument?FT=D&date=20100302&DB=&locale=en_EP&CC=US&NR=7671641B1&KC=B1&ND=1#

1 Patent

Frequency Divider
Leenaerts, D. M. W. (Inventor), Nauta, B. (Inventor) & Acar, M. (Inventor), 1 Dec 2005, Patent No. WO2005091506 (A8), Priority date 4 Mar 2005, Priority No. EP20040100996 2004011
Research output: Patent

Open Access
File

Cite this

@misc{6f8496dfdce14ff18f18750aaa54235c,

title = "Frequency divider",

abstract = "A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.",

keywords = "IR-102633, METIS-237874, EWI-8932",

author = "M. Acar and Bram Nauta and Leenaerts, {Dominicus Martinus Wilhelmus}",

year = "2010",

month = mar,

day = "2",

language = "Undefined",

type = "Patent",

note = "US7671641 B1",

}

TY - PAT

T1 - Frequency divider

AU - Acar, M.

AU - Nauta, Bram

AU - Leenaerts, Dominicus Martinus Wilhelmus

PY - 2010/3/2

Y1 - 2010/3/2

N2 - A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.

AB - A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.

KW - IR-102633

KW - METIS-237874

KW - EWI-8932

M3 - Patent

M1 - US7671641 B1

ER -

Frequency divider

Abstract

Keywords

Access to Document

Research output

Frequency Divider

Cite this