A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.
|Patent number||US7671641 B1|
|Publication status||Published - 2 Mar 2010|