Frequency Synthesiser

Salvatore Drago; Fabio Sebastiano; Dominicus M.W. Leenaerts; Lucien J. Breems; Bram  Nauta

Frequency Synthesiser

Salvatore Drago (Inventor)
, Fabio Sebastiano (Inventor)
, Dominicus M.W. Leenaerts (Inventor)
, Lucien J. Breems (Inventor)
, Bram Nauta (Inventor)

Research output: Patent

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Abstract

A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

Original language	English
Patent number	US 9240772 (B2)
Priority date	3/04/09
Publication status	Published - 19 Jan 2016

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Frequency synthesiser
Drago, S. (Inventor), Sebastiano, F. (Inventor), Leenaerts, D. M. W. (Inventor), Breems, L. J. (Inventor) & Nauta, B. (Inventor), 7 Jul 2012, Patent No. US2012 0139587 A1, Priority date 3 Apr 2009, Priority No. EP20090157284 20090403
Research output: Patent

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title = "Frequency Synthesiser",

abstract = "A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).",

author = "Salvatore Drago and Fabio Sebastiano and Leenaerts, \{Dominicus M.W.\} and Breems, \{Lucien J.\} and Bram Nauta",

year = "2016",

month = jan,

day = "19",

language = "English",

type = "Patent",

note = "US 9240772 (B2)",

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TY - PAT

T1 - Frequency Synthesiser

AU - Drago, Salvatore

AU - Sebastiano, Fabio

AU - Leenaerts, Dominicus M.W.

AU - Breems, Lucien J.

AU - Nauta, Bram

PY - 2016/1/19

Y1 - 2016/1/19

N2 - A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

AB - A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

M3 - Patent

M1 - US 9240772 (B2)

ER -

Frequency Synthesiser

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Frequency synthesiser

Cite this