There has been a growing demand for wireless communications and diverse communication standards have been developed over time, e.g. GSM, Bluetooth, Wi-Fi, etc. For convenience of use, people desire a universal radio to be able to communicate anywhere using any standard. A software-defined radio (SDR) which aims at greater programmability can meet such a demand. However, there are a number of technical challenges to make a SDR receiver practical. This thesis focuses on frequency translation (FT) techniques and addresses two key SDR challenges: the robustness to out-of-band interference (OBI) and the compatibility with CMOS scaling and system-on-chip (SoC) integration. The thesis studies the principles and the performance limitations of existing FT techniques and proposes new circuit-and-system techniques to improve SDR receivers. Fundamental differences between various FT techniques are highlighted by means of a classification and comparison of mixing and sampling. This leads to the definition of a new discrete-time (DT) mixing technique. The suitability of RFmixing and RF-sampling receivers to SDR is evaluated. RF sampling seems to be more compatible with CMOS scaling and SoC integration. However, existing RFsampling techniques are narrowband and are not directly suitable for a wideband SDR receiver. To address this issue, a DT-mixing technique is proposed which performs a mixing operation in the DT domain after RF sampling. It can make RF sampling more suitable to wideband SDR receivers because it has two properties: wideband phase shifting and wideband harmonic rejection (HR). DT mixing can be realized using de-multiplexing of samples. To verify the concept, a 200-to-900MHz DT-mixing downconverter with 8-times oversampling and 2nd-to-6th HR is implemented in 65nm CMOS. To construct a complete RF-sampling receiver, a tunable LC filter and a linearized low-noise amplifier (LNA) are applied as pre-stages of the DTVIII mixing downconverter. The LC filter employs an external coil and on-chip switchable capacitors. The LNA employs cascaded inverter stages linearized via an enhanced voltage mirror. The RF-sampling receiver achieves a minimum NF as low as 0.8dB and improves HR by 30dB compared to the downconverter alone. To be more robust to OBI, two FT techniques are proposed: one to improve the out-of-band linearity and the other to make the HR robust to mismatch. A low-pass blocker filtering technique is proposed to avoid voltage gain at radio frequencies (RF) but make voltage gain only at baseband simultaneously with low-pass filtering to attenuate OBI. The low voltage gain at RF is realized by means of a low â€œmix-impedanceï¿½?, which is analyzed quantitatively. A 2-stage polyphase HR technique is proposed to perform HR in cascaded stages to dramatically improve the amplitude accuracy. To also achieve the high phase accuracy, a simple and accurate frequency divider is presented. The effects of random amplitude and phase errors to HR are analyzed. To demonstrate these concepts, a 65nm CMOS receiver based on RF mixing shows +3.5dBm in-band IIP3 and +16dBm out-of-band IIP3. More than 60dB HR ratio is measured over 40 randomly-selected chips. The multiphase clock generator works up to 0.9GHz while the -3dB RF bandwidth is measured up to 6GHz.
|Award date||12 Nov 2009|
|Place of Publication||Enschede|
|Publication status||Published - 12 Nov 2009|