Full chip modelling of ICs under CDM stress

M.S.B. Sowariraj

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    64 Downloads (Pure)

    Abstract

    In this thesis, CDM ESD stress on the Integrated Circuits (IC) and the various factors which affect the robustness of an IC design against CDM stress is investigated. One of the main reasons for CDM failure are the voltage gradients set across the circuit during CDM stress. The IC being also the source, its discharge current path is not constrained near the input and output pads as in other kinds of ESD stress. Instead it can be anywhere through the internal circuitry into the ground. The major hinderance in developing a CDM robust protection design is the lack of knowledge on the CDM current and its discharge path through the circuit. CDM withstand level, is package dependent and it is impossible to characterize a circuit design to be CDM robust independent of its package type.
    Original languageEnglish
    Supervisors/Advisors
    • Kuper, F.G., Supervisor
    • Mouthaan, A.J., Advisor
    Thesis sponsors
    Award date9 Jun 2005
    Place of PublicationEnschede
    Publisher
    Print ISBNs90-365-2217-X
    Publication statusPublished - 9 Jun 2005

    Keywords

    • EWI-15716
    • METIS-227986
    • IR-50780

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