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Full chip modelling of ICs under CDM stress
M.S.B. Sowariraj
Research output
:
Thesis
›
PhD Thesis - Research UT, graduation UT
209
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Dive into the research topics of 'Full chip modelling of ICs under CDM stress'. Together they form a unique fingerprint.
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Engineering
Integrated Circuit
100%
Networks (Circuits)
100%
Internals
50%
Integrated Circuit Design
50%
Failure (Mechanical)
50%
Electric Potential
50%
Main Reason
50%
Circuit Design
50%
Physics
Integrated Circuit
100%
Knowledge
33%
Electric Potential
33%
Failure
33%
Output
33%
Material Science
Electronic Circuit
100%