Future Computing Platform Design: A Cross-Layer Design Approach

Hsiang Yun Cheng, Chun Feng Wu, Christian Hakert, Kuan Hsun Chen, Yuan Hao Chang, Jian Jia Chen, Chia Lin Yang, Tei Wei Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Future computing platforms are facing a paradigm shift with the emerging resistive memory technologies. First, they offer fast memory accesses and data persistence in a single large-capacity device deployed on the memory bus, blurring the boundary between memory and storage. Second, they enable computing-in-memory for neuromorphic computing to mitigate costly data movements. Due to the non-ideality of these resistive memory devices at the moment, we envision that cross-layer design is essential to bring such a system into practice. In this paper, we showcase a few examples to demonstrate how cross-layer design can be developed to fully exploit the potential of resistive memories and accelerate its adoption for future computing platforms.

Original languageEnglish
Title of host publicationProceedings of the 2021 Design, Automation and Test in Europe, DATE 2021
PublisherIEEE
Pages312-317
Number of pages6
ISBN (Electronic)9783981926354
ISBN (Print)978-1-7281-6336-9
DOIs
Publication statusPublished - 1 Feb 2021
Externally publishedYes
Event2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021 - Virtual, Online
Duration: 1 Feb 20215 Feb 2021

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume2021-February
ISSN (Print)1530-1591

Conference

Conference2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021
CityVirtual, Online
Period1/02/215/02/21

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