Gap-closing test structures for temperature budget determination

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Abstract

    We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.
    Original languageUndefined
    Title of host publication24th International Conference on Microelectronic Test Structures, ICMTS 2011
    Place of PublicationUSA
    PublisherIEEE Electron Devices Society
    Pages165-169
    Number of pages5
    ISBN (Print)978-1-4244-8527-7
    DOIs
    Publication statusPublished - 4 Apr 2011
    Event24th International Conference on Microelectronic Test Structures, ICMTS 2011 - Amsterdam, Netherlands
    Duration: 4 Apr 20117 Apr 2011
    Conference number: 24
    http://www.homepages.ed.ac.uk/ajw/ICMTS/prog11.pdf

    Publication series

    Name
    PublisherIEEE Electron Devices Society
    ISSN (Print)1071-9032

    Conference

    Conference24th International Conference on Microelectronic Test Structures, ICMTS 2011
    Abbreviated titleICMTS
    CountryNetherlands
    CityAmsterdam
    Period4/04/117/04/11
    Internet address

    Keywords

    • METIS-278716
    • EWI-20197
    • IR-77947

    Cite this

    Faber, E. J., Wolters, R. A. M., & Schmitz, J. (2011). Gap-closing test structures for temperature budget determination. In 24th International Conference on Microelectronic Test Structures, ICMTS 2011 (pp. 165-169). USA: IEEE Electron Devices Society. https://doi.org/10.1109/ICMTS.2011.5976840
    Faber, Erik Jouwert ; Wolters, Robertus A.M. ; Schmitz, Jurriaan. / Gap-closing test structures for temperature budget determination. 24th International Conference on Microelectronic Test Structures, ICMTS 2011. USA : IEEE Electron Devices Society, 2011. pp. 165-169
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    title = "Gap-closing test structures for temperature budget determination",
    abstract = "We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.",
    keywords = "METIS-278716, EWI-20197, IR-77947",
    author = "Faber, {Erik Jouwert} and Wolters, {Robertus A.M.} and Jurriaan Schmitz",
    note = "10.1109/ICMTS.2011.5976840",
    year = "2011",
    month = "4",
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    doi = "10.1109/ICMTS.2011.5976840",
    language = "Undefined",
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    publisher = "IEEE Electron Devices Society",
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    address = "United States",

    }

    Faber, EJ, Wolters, RAM & Schmitz, J 2011, Gap-closing test structures for temperature budget determination. in 24th International Conference on Microelectronic Test Structures, ICMTS 2011. IEEE Electron Devices Society, USA, pp. 165-169, 24th International Conference on Microelectronic Test Structures, ICMTS 2011, Amsterdam, Netherlands, 4/04/11. https://doi.org/10.1109/ICMTS.2011.5976840

    Gap-closing test structures for temperature budget determination. / Faber, Erik Jouwert; Wolters, Robertus A.M.; Schmitz, Jurriaan.

    24th International Conference on Microelectronic Test Structures, ICMTS 2011. USA : IEEE Electron Devices Society, 2011. p. 165-169.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    N2 - We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.

    AB - We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.

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    Faber EJ, Wolters RAM, Schmitz J. Gap-closing test structures for temperature budget determination. In 24th International Conference on Microelectronic Test Structures, ICMTS 2011. USA: IEEE Electron Devices Society. 2011. p. 165-169 https://doi.org/10.1109/ICMTS.2011.5976840