Gap-closing test structures for temperature budget determination

Erik Jouwert Faber; Robertus A.M. Wolters; Jurriaan Schmitz

doi:10.1109/ICMTS.2011.5976840

Gap-closing test structures for temperature budget determination

Erik Jouwert Faber, Robertus A.M. Wolters, Jurriaan Schmitz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.

Original language	Undefined
Title of host publication	24th International Conference on Microelectronic Test Structures, ICMTS 2011
Place of Publication	USA
Publisher	IEEE
Pages	165-169
Number of pages	5
ISBN (Print)	978-1-4244-8527-7
DOIs	https://doi.org/10.1109/ICMTS.2011.5976840
Publication status	Published - 4 Apr 2011
Event	24th International Conference on Microelectronic Test Structures, ICMTS 2011 - Amsterdam, Netherlands Duration: 4 Apr 2011 → 7 Apr 2011 Conference number: 24 http://www.homepages.ed.ac.uk/ajw/ICMTS/prog11.pdf

Publication series

Name
Publisher	IEEE Electron Devices Society
ISSN (Print)	1071-9032

Conference

Conference	24th International Conference on Microelectronic Test Structures, ICMTS 2011
Abbreviated title	ICMTS
Country/Territory	Netherlands
City	Amsterdam
Period	4/04/11 → 7/04/11
Internet address	http://www.homepages.ed.ac.uk/ajw/ICMTS/prog11.pdf

Keywords

METIS-278716
EWI-20197
IR-77947

Access to Document

10.1109/ICMTS.2011.5976840

http://eprints.eemcs.utwente.nl/secure2/20197/01/9.1_faber.pdf

Cite this

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title = "Gap-closing test structures for temperature budget determination",

abstract = "We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.",

keywords = "METIS-278716, EWI-20197, IR-77947",

author = "Faber, {Erik Jouwert} and Wolters, {Robertus A.M.} and Jurriaan Schmitz",

note = "10.1109/ICMTS.2011.5976840 ; 24th International Conference on Microelectronic Test Structures, ICMTS 2011 ; Conference date: 04-04-2011 Through 07-04-2011",

year = "2011",

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day = "4",

doi = "10.1109/ICMTS.2011.5976840",

language = "Undefined",

isbn = "978-1-4244-8527-7",

publisher = "IEEE",

pages = "165--169",

booktitle = "24th International Conference on Microelectronic Test Structures, ICMTS 2011",

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TY - GEN

T1 - Gap-closing test structures for temperature budget determination

AU - Faber, Erik Jouwert

AU - Wolters, Robertus A.M.

AU - Schmitz, Jurriaan

N1 - Conference code: 24

PY - 2011/4/4

Y1 - 2011/4/4

N2 - We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.

AB - We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.

KW - METIS-278716

KW - EWI-20197

KW - IR-77947

U2 - 10.1109/ICMTS.2011.5976840

DO - 10.1109/ICMTS.2011.5976840

M3 - Conference contribution

SN - 978-1-4244-8527-7

SP - 165

EP - 169

BT - 24th International Conference on Microelectronic Test Structures, ICMTS 2011

PB - IEEE

CY - USA

T2 - 24th International Conference on Microelectronic Test Structures, ICMTS 2011

Y2 - 4 April 2011 through 7 April 2011

ER -