Gate-capacitance extraction from RF C-V measurements

G.T. Sasse, R. de Kort, Jurriaan Schmitz

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    3 Citations (Scopus)
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    Abstract

    n this work, a full two-port analysis of an RF C-V measurement set-up is given. This two-port analysis gives insight on the limitations of the commonly used gate capacitance extraction, based on the Y/sub 11/ parameter of the device. It is shown that the parasitics of the device can disturb the extracted gate capacitance and a new extraction scheme, based on the Z-matrix, is introduced that eliminates the effect of these parasitics. Measurement results prove the validity of this new extraction scheme, under different conditions.
    Original languageUndefined
    Title of host publicationThe 34th European Solid-State Device Research conference, 2004
    Place of PublicationPiscataway
    PublisherIEEE
    Pages113-116
    Number of pages4
    ISBN (Print)0780384784
    DOIs
    Publication statusPublished - 15 Nov 2004
    Event34th European Solid-State Device Research Conference, ESSDERC 2004 - Leuven, Belgium
    Duration: 21 Sep 200423 Sep 2004
    Conference number: 34

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference34th European Solid-State Device Research Conference, ESSDERC 2004
    Abbreviated titleESSDERC
    CountryBelgium
    CityLeuven
    Period21/09/0423/09/04

    Keywords

    • IR-47970
    • MIS devices
    • EWI-15535
    • impedance matrix
    • METIS-219035
    • Semiconductor device measurement
    • Capacitance measurement

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