Gate Current and Oxide Reliability in p+ Poly MOS Capacitors with Poly-Si and Poly-Ge0.3 Si0.7 Gate Material

Cora Salm, J.H. Klootwijk, Y. Ponomarev, P.W.M. Boos, P.W.M. Boos, D.J. Gravesteijn, P.H. Woerlee

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    Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge0.3Si0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, ¿B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Qbd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability
    Original languageUndefined
    Pages (from-to)213-215
    Number of pages3
    JournalIEEE electron device letters
    Issue number19
    Publication statusPublished - 1998


    • METIS-112012
    • IR-15140

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