Gate Delay Fault Test Generation for Non-Scan Circuits

G. van Brakel, G. van Brakel, U. Gläser, Hans G. Kerkhoff, H.T. Vierhaus

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    Abstract

    This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation-backward justification technique: The test pattern generation is started at the fault location, and after successful ¿local¿ test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this paper
    Original languageUndefined
    Title of host publicationProceedings of the IEEE European Design and Test Conference, ED&TC 1995
    Place of PublicationParijs
    PublisherIEEE
    Pages308-312
    ISBN (Print)9780818670398
    DOIs
    Publication statusPublished - 6 Mar 1995

    Publication series

    Name
    PublisherIEEE

    Keywords

    • METIS-112928
    • IR-16044

    Cite this

    van Brakel, G., van Brakel, G., Gläser, U., Kerkhoff, H. G., & Vierhaus, H. T. (1995). Gate Delay Fault Test Generation for Non-Scan Circuits. In Proceedings of the IEEE European Design and Test Conference, ED&TC 1995 (pp. 308-312). Parijs: IEEE. https://doi.org/10.1109/EDTC.1995.470379