Gate dielectrics for high performance and low power CMOS SoC applications

F. Cubaynes*, C.J.J. Dachs, C. Detcheverry, A. Zegers, V.C. Venezia, J. Schmitz, P.A. Stolk, M. Jurczak, K. Henson, R. Degraeve, A. Rothschild, T. Conard, J. Petry, M. Da Rold, M. Schaekers, G. Badenes, L. Date, D. Pique, H.N. Al-Shareef, R.W. Murto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

Original languageEnglish
Title of host publicationESSDERC 2002
Subtitle of host publicationProceedings of the 32nd European Solid-State Device Research Conference, Firenze, Italy, 24-26 September 2002
EditorsElena Gnani, Giorgio Baccarani, Massimo Rudan
Place of PublicationPiscataway, NJ
PublisherIEEE Computer Society
Pages427-430
Number of pages4
ISBN (Print)88-900847-8-2
DOIs
Publication statusPublished - 1 Jan 2002
Externally publishedYes
Event32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy
Duration: 24 Sep 200226 Sep 2002
Conference number: 32

Conference

Conference32nd European Solid-State Device Research Conference, ESSDERC 2002
Abbreviated titleESSDERC
CountryItaly
CityFirenze
Period24/09/0226/09/02

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