Gate-Level Test Implementation for Optimal Area/Throughput/Test in VLIW TTA Architectures

V. Zivkovic, R.J.W.T. Tangelder, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Original languageUndefined
    Title of host publicationProceedings of Prorisc 2000
    Place of PublicationVeldhoven, The Netherlands
    Pages595-601
    Publication statusPublished - 30 Nov 2000

    Keywords

    • METIS-113008

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