Gate oxide reliability and deuterated CMOS processing

A.J. Hof, A. Kovalgin, R. van Schaijk, W.M. Baks, J. Schmitz

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

40 Downloads (Pure)

Abstract

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories.
Original languageEnglish
Title of host publicationIEEE Integrated Reliability Workshop 2004
Place of PublicationPiscataway, NJ
PublisherIEEE Computer Society
Pages7-10
Number of pages4
ISBN (Print)0-7803-8517-9
DOIs
Publication statusPublished - 25 Apr 2004
EventIEEE Integrated Reliability Workshop 2004 - South Lake Tahoe, United States
Duration: 18 Oct 200421 Oct 2004

Conference

ConferenceIEEE Integrated Reliability Workshop 2004
CountryUnited States
CitySouth Lake Tahoe
Period18/10/0421/10/04

Fingerprint

Deuterium
Oxides
Processing
Isotopes
Hot carriers
Gate dielectrics
Metals
Degradation
Oxidation

Keywords

  • MIS devices
  • CMOS integrated circuits
  • Deuterium
  • Dielectric thin films
  • Annealing

Cite this

Hof, A. J., Kovalgin, A., van Schaijk, R., Baks, W. M., & Schmitz, J. (2004). Gate oxide reliability and deuterated CMOS processing. In IEEE Integrated Reliability Workshop 2004 (pp. 7-10). Piscataway, NJ: IEEE Computer Society. https://doi.org/10.1109/IRWS.2004.1422727
Hof, A.J. ; Kovalgin, A. ; van Schaijk, R. ; Baks, W.M. ; Schmitz, J. / Gate oxide reliability and deuterated CMOS processing. IEEE Integrated Reliability Workshop 2004. Piscataway, NJ : IEEE Computer Society, 2004. pp. 7-10
@inproceedings{b50e4a56fc154fac97e1e89ae19e1a3f,
title = "Gate oxide reliability and deuterated CMOS processing",
abstract = "In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories.",
keywords = "MIS devices, CMOS integrated circuits, Deuterium, Dielectric thin films, Annealing",
author = "A.J. Hof and A. Kovalgin and {van Schaijk}, R. and W.M. Baks and J. Schmitz",
year = "2004",
month = "4",
day = "25",
doi = "10.1109/IRWS.2004.1422727",
language = "English",
isbn = "0-7803-8517-9",
pages = "7--10",
booktitle = "IEEE Integrated Reliability Workshop 2004",
publisher = "IEEE Computer Society",
address = "United States",

}

Hof, AJ, Kovalgin, A, van Schaijk, R, Baks, WM & Schmitz, J 2004, Gate oxide reliability and deuterated CMOS processing. in IEEE Integrated Reliability Workshop 2004. IEEE Computer Society, Piscataway, NJ, pp. 7-10, IEEE Integrated Reliability Workshop 2004, South Lake Tahoe, United States, 18/10/04. https://doi.org/10.1109/IRWS.2004.1422727

Gate oxide reliability and deuterated CMOS processing. / Hof, A.J.; Kovalgin, A.; van Schaijk, R.; Baks, W.M.; Schmitz, J.

IEEE Integrated Reliability Workshop 2004. Piscataway, NJ : IEEE Computer Society, 2004. p. 7-10.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Gate oxide reliability and deuterated CMOS processing

AU - Hof, A.J.

AU - Kovalgin, A.

AU - van Schaijk, R.

AU - Baks, W.M.

AU - Schmitz, J.

PY - 2004/4/25

Y1 - 2004/4/25

N2 - In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories.

AB - In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories.

KW - MIS devices

KW - CMOS integrated circuits

KW - Deuterium

KW - Dielectric thin films

KW - Annealing

U2 - 10.1109/IRWS.2004.1422727

DO - 10.1109/IRWS.2004.1422727

M3 - Conference contribution

SN - 0-7803-8517-9

SP - 7

EP - 10

BT - IEEE Integrated Reliability Workshop 2004

PB - IEEE Computer Society

CY - Piscataway, NJ

ER -

Hof AJ, Kovalgin A, van Schaijk R, Baks WM, Schmitz J. Gate oxide reliability and deuterated CMOS processing. In IEEE Integrated Reliability Workshop 2004. Piscataway, NJ: IEEE Computer Society. 2004. p. 7-10 https://doi.org/10.1109/IRWS.2004.1422727