Gate Oxide Reliability of Poly-Si and Poly-SiGe CMOS Devices

Vincent Etienne Houtsma

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    1610 Downloads (Pure)


    This thesis focuses on the gate oxide reliability of poly silicon (poly-Si) and poly Silicon-Germanium(poly-Si0:7Ge0:3) dual gate CMOS devices. The conduction mechanism (I-V), Stress-Induced Leakage Current (SILC) and time-tobreakdown (tbd) of these devices on (ultra-)thin gate oxides is studied. P+ and n+-gates with poly-Si and poly-SiGe are used to study the in uence of gate workfunction on gate current and SILC current. Poly-SiGe is chosen since its allows modification of the workfunction of the gate for p+-poly gate devices. Moreover, it is fully compatible with (poly-)Si technology.
    Original languageEnglish
    QualificationDoctor of Philosophy
    Awarding Institution
    • University of Twente
    • Woerlee, P.H., Supervisor
    • Holleman, J., Co-Supervisor
    Award date14 Jan 2000
    Place of PublicationEnschede, The Netherlands
    Print ISBNs90-365-1391-X
    Publication statusPublished - 14 Jan 2000


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