This thesis focuses on the gate oxide reliability of poly silicon (poly-Si) and poly Silicon-Germanium(poly-Si0:7Ge0:3) dual gate CMOS devices. The conduction mechanism (I-V), Stress-Induced Leakage Current (SILC) and time-tobreakdown (tbd) of these devices on (ultra-)thin gate oxides is studied. P+ and n+-gates with poly-Si and poly-SiGe are used to study the in uence of gate workfunction on gate current and SILC current. Poly-SiGe is chosen since its allows modification of the workfunction of the gate for p+-poly gate devices. Moreover, it is fully compatible with (poly-)Si technology.
|Award date||14 Jan 2000|
|Place of Publication||Enschede, The Netherlands|
|Publication status||Published - 14 Jan 2000|