Gate polysilicon optimization for deep-submicron MOSFETs

J. Schmitz*, H.P. Tuinhout, A.H. Montree, Y.V. Ponomarev, P.A. Stolk, P.H. Woerlee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)
39 Downloads (Pure)

Abstract

The use of amorphously deposited silicon and fine-grained polysilicon as MOS gate material is discussed. A variety of deposition and anneal conditions was evaluated on MOS capacitors and transistors. Gate depletion and MOSFET matching have been studied as a function of deposition condition and gate activation temperature. It is shown that polysilicon gate material has better properties than α-Si for CMOS generations beyond 0.18μm.

Original languageEnglish
Title of host publicationESSDERC '99
Subtitle of host publicationproceedings of the 29th European Solid-State Device Research Conference : Leuven, Belgium, 13-15 September, 1999
EditorsR.P. Mertens, H. Grünbacher, H.E. Maes, G. Declerck
Place of PublicationPiscataway, NJ
PublisherIEEE Computer Society
Pages156-159
Number of pages4
ISBN (Print)2-86332-245-1
Publication statusPublished - 1 Jan 1999
Externally publishedYes
Event29th European Solid-State Device Research Conference, ESSDERC 1999 - Leuven, Belgium
Duration: 13 Sep 199915 Sep 1999
Conference number: 29

Conference

Conference29th European Solid-State Device Research Conference, ESSDERC 1999
Abbreviated titleESSDERC
CountryBelgium
CityLeuven
Period13/09/9915/09/99

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