Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 μm CMOS technology

Y. V. Ponomarev*, C. Salm, J. Schmitz, P. H. Woerlee, P. A. Stolk, D. J. Gravesteijn

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 μm devices are manufactured using p- and n-type poly-Si/Si0.8Ge0.2 gates.

Original languageEnglish
Title of host publicationInternational Electron Devices Meeting, 1997, Washington, DC, December 7-10, 1997
Subtitle of host publicationIEDM Technical Digest
Place of PublicationPiscataway, NJ
Number of pages4
ISBN (Print)0-7803-4100-7
Publication statusPublished - 1997
Event1997 International Electron Devices Meeting, IEDM 1997 - Washington, United States
Duration: 7 Dec 199710 Dec 1997

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918


Conference1997 International Electron Devices Meeting, IEDM 1997
Abbreviated titleIEDM
Country/TerritoryUnited States

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