Gate-Workfunction Engineering Using Poly-(Si,Ge) for High-Performance 0.18um CMOS Technology

Y.V. Ponomarev, C. Salm, Jurriaan Schmitz, P.H. Woerlee, P.A. Stolk, D.J. Gravesteijn

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    Abstract

    We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 µm devices are manufactured using p- and n-type poly-Si/Si0.8Ge 0.2 gates
    Original languageEnglish
    Title of host publicationInternational Electron Devices Meeting, 1997, Washington, DC, December 7-10, 1997
    Subtitle of host publicationIEDM Technical Digest
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages829-832
    Number of pages4
    ISBN (Print)0-7803-4100-7, 0-7803-4101-5
    DOIs
    Publication statusPublished - 1 Dec 1997
    Event1997 International Electron Devices Meeting, IEDM 1997 - Washington, United States
    Duration: 7 Dec 199710 Dec 1997

    Publication series

    NameInternational Electron Devices Meeting, IEDM Technical Digest
    PublisherIEEE
    Volume1997
    ISSN (Print)0163-1918

    Conference

    Conference1997 International Electron Devices Meeting, IEDM 1997
    Abbreviated titleIEDM
    CountryUnited States
    CityWashington
    Period7/12/9710/12/97

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