Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

Anuradha Chathuranga Ranasinghe, Sabih H. Gerez

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)
2 Downloads (Pure)

Abstract

This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.
Original languageEnglish
Article number9149668
Pages (from-to)2028-2041
Number of pages14
JournalIEEE transactions on very large scale integration (VLSI) systems
Volume28
Issue number9
Early online date27 Jul 2020
DOIs
Publication statusPublished - Sep 2020

Keywords

  • Alternative logic styles
  • Booth multipliers
  • CMOS
  • Wallace tree
  • XOR-XNR
  • array multipliers
  • glitch reduction
  • spurious activities
  • 22/2 OA procedure

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