TY - JOUR
T1 - Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers
AU - Anuradha Chathuranga Ranasinghe, null
AU - Gerez, Sabih H.
N1 - Funding Information:
Manuscript received May 5, 2020; accepted June 21, 2020. Date of publication July 27, 2020; date of current version August 26, 2020. This work was supported in part by the Dutch NWO Applied and Engineering Sciences program ZERO: Towards Energy Autonomous Systems for IoT and in part by Dialog Semiconductor B.V., The Netherlands. (Corresponding author: Anuradha Chathuranga Ranasinghe.) The authors are with the Chair of Computer Architecture for Embedded Systems, University of Twente, 7522 NB Enschede, The Netherlands (e-mail: [email protected]).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.
AB - This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.
KW - Alternative logic styles
KW - Booth multipliers
KW - CMOS
KW - Wallace tree
KW - XOR-XNR
KW - array multipliers
KW - glitch reduction
KW - spurious activities
KW - 22/2 OA procedure
UR - http://www.scopus.com/inward/record.url?scp=85090453785&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2020.3009239
DO - 10.1109/TVLSI.2020.3009239
M3 - Article
SN - 1063-8210
VL - 28
SP - 2028
EP - 2041
JO - IEEE transactions on very large scale integration (VLSI) systems
JF - IEEE transactions on very large scale integration (VLSI) systems
IS - 9
M1 - 9149668
ER -