Global On-Chip Differential Interconnects with Optimally-Placed Twists

Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects of only 0.8 μm pitch. These small interconnects suffer from severe inter-symbol interference due to their high distributed resistance and capacitance. By using pulse-width equalization and low-ohmic termination, the inter-symbol interference is reduced and the achievable data rate is increased from 0.55 Gb/s/ch to 3 Gb/s/ch. Next to inter-symbol interference, the interconnects also suffer from crosstalk from neighboring interconnects. Analysis and measurements show that this crosstalk would impede the achievable data rate if it were not mitigated. In order to cancel the crosstalk, one twist is placed in every even interconnect in the bus and two twists are placed in every odd interconnect in the bus. Analysis shows that there are optimal positions for these twists, depending on the termination of the interconnects. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.