Graphics algorithms on field programmable function arrays

Jaap Smit; Marco Bosma

doi:10.2312/EGGH/EGGH96/103-108

Graphics algorithms on field programmable function arrays

Jaap Smit, Marco Bosma

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.

Original language	English
Title of host publication	Proceedings of the 11th Eurographics Workshop on Graphics Hardware
Subtitle of host publication	25th and 26th August 1996
Publisher	Eurographics Association
Pages	103-108
Number of pages	6
DOIs	https://doi.org/10.2312/EGGH/EGGH96/103-108
Publication status	Published - 26 Aug 1996
Event	11th Eurographics Workshop on Graphics Hardware, EGGH 1996 - Poitiers, France Duration: 26 Aug 1996 → 27 Aug 1996 Conference number: 11

Publication series

Name	Eurographics technical report series
Publisher	The Eurographics Association
Number	EG 96 HW

Conference

Conference	11th Eurographics Workshop on Graphics Hardware, EGGH 1996
Abbreviated title	EGGH96
Country/Territory	France
City	Poitiers
Period	26/08/96 → 27/08/96

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10.2312/EGGH/EGGH96/103-108

Smit1996graphicsFinal published version, 574 KB

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@inproceedings{56eeeae2f21941b3a73c1dce25963ba4,

title = "Graphics algorithms on field programmable function arrays",

abstract = "The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.",

author = "Jaap Smit and Marco Bosma",

year = "1996",

month = aug,

day = "26",

doi = "10.2312/EGGH/EGGH96/103-108",

language = "English",

series = "Eurographics technical report series",

publisher = "Eurographics Association",

number = "EG 96 HW",

pages = "103--108",

booktitle = "Proceedings of the 11th Eurographics Workshop on Graphics Hardware",

address = "Switzerland",

note = "11th Eurographics Workshop on Graphics Hardware, EGGH 1996, EGGH96 ; Conference date: 26-08-1996 Through 27-08-1996",

}

Smit, J & Bosma, M 1996, Graphics algorithms on field programmable function arrays. in Proceedings of the 11th Eurographics Workshop on Graphics Hardware: 25th and 26th August 1996. Eurographics technical report series, no. EG 96 HW, Eurographics Association, pp. 103-108, 11th Eurographics Workshop on Graphics Hardware, EGGH 1996, Poitiers, France, 26/08/96. https://doi.org/10.2312/EGGH/EGGH96/103-108

Graphics algorithms on field programmable function arrays. / Smit, Jaap; Bosma, Marco.
Proceedings of the 11th Eurographics Workshop on Graphics Hardware: 25th and 26th August 1996. Eurographics Association, 1996. p. 103-108 (Eurographics technical report series; No. EG 96 HW).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Graphics algorithms on field programmable function arrays

AU - Smit, Jaap

AU - Bosma, Marco

N1 - Conference code: 11

PY - 1996/8/26

Y1 - 1996/8/26

N2 - The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.

AB - The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.

U2 - 10.2312/EGGH/EGGH96/103-108

DO - 10.2312/EGGH/EGGH96/103-108

M3 - Conference contribution

T3 - Eurographics technical report series

SP - 103

EP - 108

BT - Proceedings of the 11th Eurographics Workshop on Graphics Hardware

PB - Eurographics Association

T2 - 11th Eurographics Workshop on Graphics Hardware, EGGH 1996

Y2 - 26 August 1996 through 27 August 1996

ER -

Graphics algorithms on field programmable function arrays

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