Graphics algorithms on field programmable function arrays

Jaap Smit, Marco Bosma

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    Abstract

    The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.
    Original languageEnglish
    Title of host publicationProceedings of the 11th Eurographics Workshop on Graphics Hardware
    Subtitle of host publication25th and 26th August 1996
    PublisherEurographics Association
    Pages103-108
    Number of pages6
    DOIs
    Publication statusPublished - 26 Aug 1996
    Event11th Eurographics Workshop on Graphics Hardware, EGGH 1996 - Poitiers, France
    Duration: 26 Aug 199627 Aug 1996
    Conference number: 11

    Publication series

    NameEurographics technical report series
    PublisherThe Eurographics Association
    NumberEG 96 HW

    Conference

    Conference11th Eurographics Workshop on Graphics Hardware, EGGH 1996
    Abbreviated titleEGGH96
    CountryFrance
    CityPoitiers
    Period26/08/9627/08/96

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