Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

A.C. Dam, M.G.J. Lammertink, K.C. Rovers, J. Slagman, A.M. Wellink, G.K. Rauwerda, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    1 Citation (Scopus)
    202 Downloads (Pure)


    This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient.
    Original languageUndefined
    Title of host publicationProceedings of the 9th EUROMICRO Conference on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2006)
    Place of PublicationLos Alamitos
    PublisherIEEE Computer Society
    Number of pages9
    ISBN (Print)0-7695-2609-8
    Publication statusPublished - 30 Aug 2006
    Event9th EUROMICRO Conference on Digital System Design, DSD 2006: Architectures, Methods and Tools - Dubrovnik, Croatia
    Duration: 30 Aug 20061 Sep 2006
    Conference number: 9

    Publication series

    PublisherIEEE Computer Society


    Conference9th EUROMICRO Conference on Digital System Design, DSD 2006
    Abbreviated titleDSD


    • EWI-6170
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-238097
    • IR-66208

    Cite this