Abstract
This paper addresses the implementation of Reed-
Solomon decoding for battery-powered wireless
devices. The scope of this paper is constrained by the
Digital Media Broadcasting (DMB). The most critical
element of the Reed-Solomon algorithm is implemented
on two different reconfigurable hardware
architectures: an FPGA and a coarse-grained
architecture: the Montium, The remaining parts are
executed on an ARM processor. The results of this
research show that a co-design of the ARM together
with an FPGA or a Montium leads to a substantial
decrease in energy consumption. The energy
consumption of syndrome calculation of the Reed-
Solomon decoding algorithm is estimated for an FPGA
and a Montium by means of simulations. The Montium
proves to be more efficient.
Original language | Undefined |
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Title of host publication | Proceedings of the 9th EUROMICRO Conference on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2006) |
Place of Publication | Los Alamitos |
Publisher | IEEE Computer Society |
Pages | 447-455 |
Number of pages | 9 |
ISBN (Print) | 0-7695-2609-8 |
DOIs | |
Publication status | Published - 30 Aug 2006 |
Event | 9th EUROMICRO Conference on Digital System Design, DSD 2006: Architectures, Methods and Tools - Dubrovnik, Croatia Duration: 30 Aug 2006 → 1 Sep 2006 Conference number: 9 |
Publication series
Name | |
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Publisher | IEEE Computer Society |
Number | 2 |
Conference
Conference | 9th EUROMICRO Conference on Digital System Design, DSD 2006 |
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Abbreviated title | DSD |
Country/Territory | Croatia |
City | Dubrovnik |
Period | 30/08/06 → 1/09/06 |
Keywords
- EWI-6170
- CAES-EEA: Efficient Embedded Architectures
- METIS-238097
- IR-66208