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Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

  • Arjan C. Dam
  • , Michel G.J. Lammertink
  • , Kenneth C. Rovers
  • , Johan Slagman
  • , Arno M. Wellink
  • , Gerard K. Rauwerda
  • , Gerard J.M. Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    479 Downloads (Pure)

    Abstract

    This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient.
    Original languageEnglish
    Title of host publicationProceedings of the 9th EUROMICRO Conference on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2006)
    Place of PublicationLos Alamitos, CA
    PublisherIEEE
    Pages447-455
    Number of pages9
    Volume2
    ISBN (Print)0-7695-2609-8
    DOIs
    Publication statusPublished - 30 Aug 2006
    Event9th EUROMICRO Conference on Digital System Design, DSD 2006: Architectures, Methods and Tools - Dubrovnik, Croatia
    Duration: 30 Aug 20061 Sept 2006
    Conference number: 9

    Conference

    Conference9th EUROMICRO Conference on Digital System Design, DSD 2006
    Abbreviated titleDSD
    Country/TerritoryCroatia
    CityDubrovnik
    Period30/08/061/09/06

    Keywords

    • CAES-EEA: Efficient Embedded Architectures
    • n/a OA procedure

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