Hierarchical statical verification of large full custom CMOS circuits

A.B. van der Wal; R.G.J. Arendsen; O.E. Herrmann; A.C. Brombacher

doi:10.1109/ISCAS.1994.408834

Hierarchical statical verification of large full custom CMOS circuits

A.B. van der Wal, R.G.J. Arendsen, O.E. Herrmann, A.C. Brombacher

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.

Original language	English
Title of host publication	Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94
Place of Publication	Los Alamitos, CA
Publisher	IEEE
Pages	443-446
ISBN (Print)	0-7803-1915-X
DOIs	https://doi.org/10.1109/ISCAS.1994.408834
Publication status	Published - 1995
Event	IEEE International Symposium on Circuits and Systems, ISCAS 1994 - London, United Kingdom Duration: 30 May 1994 → 2 Jun 1994

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 1994
Abbreviated title	ISCAS
Country/Territory	United Kingdom
City	London
Period	30/05/94 → 2/06/94

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10.1109/ISCAS.1994.408834

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title = "Hierarchical statical verification of large full custom CMOS circuits",

abstract = "This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.",

author = "{van der Wal}, A.B. and R.G.J. Arendsen and O.E. Herrmann and A.C. Brombacher",

year = "1995",

doi = "10.1109/ISCAS.1994.408834",

language = "English",

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pages = "443--446",

booktitle = "Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94",

publisher = "IEEE",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 1994, ISCAS ; Conference date: 30-05-1994 Through 02-06-1994",

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van der Wal, AB, Arendsen, RGJ, Herrmann, OE & Brombacher, AC 1995, Hierarchical statical verification of large full custom CMOS circuits. in Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94. IEEE, Los Alamitos, CA, pp. 443-446, IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, United Kingdom, 30/05/94. https://doi.org/10.1109/ISCAS.1994.408834

Hierarchical statical verification of large full custom CMOS circuits. / van der Wal, A.B.; Arendsen, R.G.J.; Herrmann, O.E. et al.
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94. Los Alamitos, CA: IEEE, 1995. p. 443-446.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Hierarchical statical verification of large full custom CMOS circuits

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AU - Arendsen, R.G.J.

AU - Herrmann, O.E.

AU - Brombacher, A.C.

PY - 1995

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N2 - This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.

AB - This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.

U2 - 10.1109/ISCAS.1994.408834

DO - 10.1109/ISCAS.1994.408834

M3 - Conference contribution

SN - 0-7803-1915-X

SP - 443

EP - 446

BT - Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

PB - IEEE

CY - Los Alamitos, CA

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 1994

Y2 - 30 May 1994 through 2 June 1994

ER -

Hierarchical statical verification of large full custom CMOS circuits

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