TY - JOUR
T1 - High-Linearity bottom-plate mixing technique with switch sharing for N-path filters/mixers
AU - Lien, Yuan-Ching
AU - Klumperink, Eric A.M.
AU - Tenbroek, Bernard
AU - Strange, Jon
AU - Nauta, Bram
PY - 2019/2/1
Y1 - 2019/2/1
N2 - A four-path filter/mixer for surface acoustic wave (SAW)-less frequency division duplex (FDD) radio receivers is proposed, targeting high linearity and compression requirements. A bottom-plate mixing technique improves linearity by reducing the gate-source voltage modulation of the MOSFET switches. Differential bottom-plate mixing allows for switch sharing which halves the effective switch resistance to reduce drain-source voltage modulation. The first four-path switch-RC filter stage with bottom-plate mixing and a shared switch renders 2nd-order voltage-domain RF-bandpass filtering around the LO frequency. Extra out-of-band rejection is implemented combined with V – I conversion and zero-IF frequency down-conversion in the second cross-coupled switch-RC four-path stage, which offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28-nm CMOS technology achieves an out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7-GHz LO (i.e., 6- and 9-dB blocker noise figure). The chip consumes 38–96 mW for LO-frequencies of 0.1–2 GHz and occupies an active area of 0.49 mm 2
AB - A four-path filter/mixer for surface acoustic wave (SAW)-less frequency division duplex (FDD) radio receivers is proposed, targeting high linearity and compression requirements. A bottom-plate mixing technique improves linearity by reducing the gate-source voltage modulation of the MOSFET switches. Differential bottom-plate mixing allows for switch sharing which halves the effective switch resistance to reduce drain-source voltage modulation. The first four-path switch-RC filter stage with bottom-plate mixing and a shared switch renders 2nd-order voltage-domain RF-bandpass filtering around the LO frequency. Extra out-of-band rejection is implemented combined with V – I conversion and zero-IF frequency down-conversion in the second cross-coupled switch-RC four-path stage, which offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28-nm CMOS technology achieves an out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7-GHz LO (i.e., 6- and 9-dB blocker noise figure). The chip consumes 38–96 mW for LO-frequencies of 0.1–2 GHz and occupies an active area of 0.49 mm 2
U2 - 10.1109/JSSC.2018.2878812
DO - 10.1109/JSSC.2018.2878812
M3 - Article
SN - 0018-9200
VL - 54
SP - 323
EP - 335
JO - IEEE journal of solid-state circuits
JF - IEEE journal of solid-state circuits
IS - 2
M1 - 8538881
ER -