High performance 0.13um CMOS with classical architecture

J. Schmitz*, A.C.M.C. van Brandenburg, E.J.H. Collart, L.H.M. Huijten, A.H. Montree, Y.V. Ponomarev, R.F.M. Roes, A.J. Scholten, P.H. Woerlee

*Corresponding author for this work

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Abstract

We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

Original languageEnglish
Title of host publicationESSDERC 1998
Subtitle of host publicationProceedings of the 28th European Solid-State Device Research Conference
EditorsA. Touboul, Y. Danto, H. Grünbacher
Place of PublicationPiscataway, NJ
PublisherIEEE Computer Society
Pages156-159
Number of pages4
ISBN (Electronic)2863322346
Publication statusPublished - 1 Jan 1998
Externally publishedYes
Event28th European Solid-State Device Research Conference, ESSDERC 1998 - Bordeaux, France
Duration: 8 Sep 199810 Sep 1998
Conference number: 28

Conference

Conference28th European Solid-State Device Research Conference, ESSDERC 1998
Abbreviated titleESSDERC 1998
CountryFrance
CityBordeaux
Period8/09/9810/09/98

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Schmitz, J., van Brandenburg, A. C. M. C., Collart, E. J. H., Huijten, L. H. M., Montree, A. H., Ponomarev, Y. V., ... Woerlee, P. H. (1998). High performance 0.13um CMOS with classical architecture. In A. Touboul, Y. Danto, & H. Grünbacher (Eds.), ESSDERC 1998: Proceedings of the 28th European Solid-State Device Research Conference (pp. 156-159). [1503512] Piscataway, NJ: IEEE Computer Society.