High performance 0.13um CMOS with classical architecture

J. Schmitz; A.C.M.C. van Brandenburg; E.J.H. Collart; L.H.M. Huijten; A.H. Montree; Y.V. Ponomarev; R.F.M. Roes; A.J. Scholten; P.H. Woerlee

High performance 0.13um CMOS with classical architecture

J. Schmitz^*, A.C.M.C. van Brandenburg, E.J.H. Collart, L.H.M. Huijten, A.H. Montree, Y.V. Ponomarev, R.F.M. Roes, A.J. Scholten, P.H. Woerlee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO₂ gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

Original language	English
Title of host publication	ESSDERC 1998
Subtitle of host publication	Proceedings of the 28th European Solid-State Device Research Conference
Editors	A. Touboul, Y. Danto, H. Grünbacher
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	156-159
Number of pages	4
ISBN (Electronic)	2863322346
Publication status	Published - 1 Jan 1998
Externally published	Yes
Event	28th European Solid-State Device Research Conference, ESSDERC 1998 - Bordeaux, France Duration: 8 Sept 1998 → 10 Sept 1998 Conference number: 28

Conference

Conference	28th European Solid-State Device Research Conference, ESSDERC 1998
Abbreviated title	ESSDERC 1998
Country/Territory	France
City	Bordeaux
Period	8/09/98 → 10/09/98

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Schmitz, J., van Brandenburg, A. C. M. C., Collart, E. J. H., Huijten, L. H. M., Montree, A. H., Ponomarev, Y. V., Roes, R. F. M., Scholten, A. J., & Woerlee, P. H. (1998). High performance 0.13um CMOS with classical architecture. In A. Touboul, Y. Danto, & H. Grünbacher (Eds.), ESSDERC 1998: Proceedings of the 28th European Solid-State Device Research Conference (pp. 156-159). Article 1503512 IEEE. https://ieeexplore.ieee.org/document/1503512

@inproceedings{5c83b9086cea49bba025427209e9b023,

title = "High performance 0.13um CMOS with classical architecture",

abstract = "We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.",

author = "J. Schmitz and {van Brandenburg}, A.C.M.C. and E.J.H. Collart and L.H.M. Huijten and A.H. Montree and Y.V. Ponomarev and R.F.M. Roes and A.J. Scholten and P.H. Woerlee",

year = "1998",

month = jan,

day = "1",

language = "English",

pages = "156--159",

editor = "A. Touboul and Y. Danto and H. Gr{\"u}nbacher",

booktitle = "ESSDERC 1998",

publisher = "IEEE",

address = "United States",

note = "28th European Solid-State Device Research Conference, ESSDERC 1998, ESSDERC 1998 ; Conference date: 08-09-1998 Through 10-09-1998",

}

Schmitz, J, van Brandenburg, ACMC, Collart, EJH, Huijten, LHM, Montree, AH, Ponomarev, YV, Roes, RFM, Scholten, AJ & Woerlee, PH 1998, High performance 0.13um CMOS with classical architecture. in A Touboul, Y Danto & H Grünbacher (eds), ESSDERC 1998: Proceedings of the 28th European Solid-State Device Research Conference., 1503512, IEEE, Piscataway, NJ, pp. 156-159, 28th European Solid-State Device Research Conference, ESSDERC 1998, Bordeaux, France, 8/09/98. <https://ieeexplore.ieee.org/document/1503512>

High performance 0.13um CMOS with classical architecture. / Schmitz, J.; van Brandenburg, A.C.M.C.; Collart, E.J.H. et al.
ESSDERC 1998: Proceedings of the 28th European Solid-State Device Research Conference. ed. / A. Touboul; Y. Danto; H. Grünbacher. Piscataway, NJ: IEEE, 1998. p. 156-159 1503512.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - High performance 0.13um CMOS with classical architecture

AU - Schmitz, J.

AU - van Brandenburg, A.C.M.C.

AU - Collart, E.J.H.

AU - Huijten, L.H.M.

AU - Montree, A.H.

AU - Ponomarev, Y.V.

AU - Roes, R.F.M.

AU - Scholten, A.J.

AU - Woerlee, P.H.

N1 - Conference code: 28

PY - 1998/1/1

Y1 - 1998/1/1

N2 - We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

AB - We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

UR - http://www.scopus.com/inward/record.url?scp=84908222441&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84908222441

SP - 156

EP - 159

BT - ESSDERC 1998

A2 - Touboul, A.

A2 - Danto, Y.

A2 - Grünbacher, H.

PB - IEEE

CY - Piscataway, NJ

T2 - 28th European Solid-State Device Research Conference, ESSDERC 1998

Y2 - 8 September 1998 through 10 September 1998

ER -

High performance 0.13um CMOS with classical architecture

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