High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

C. Bolchini; A. Miele; C. Sandionigi; M. Ottavi; S. Pontarelli; A. Salsano; C. Metra; M. Omaña; D. Rossi; M.S. Reorda; L. Sterpone; M. Violante; S. Gerardin; M. Bagatin; A. Paccagnella

doi:10.1109/DFT.2012.6378211

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

C. Bolchini, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omaña, D. Rossi, M.S. Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISBN (Electronic)	978-1-4673-3044-2
DOIs	https://doi.org/10.1109/DFT.2012.6378211
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 - Austin, United States Duration: 3 Oct 2012 → 5 Oct 2012

Conference

Conference	2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
Abbreviated title	DFT
Country/Territory	United States
City	Austin
Period	3/10/12 → 5/10/12

Access to Document

10.1109/DFT.2012.6378211

Cite this

Bolchini, C., Miele, A., Sandionigi, C., Ottavi, M., Pontarelli, S., Salsano, A., Metra, C., Omaña, M., Rossi, D., Reorda, M. S., Sterpone, L., Violante, M., Gerardin, S., Bagatin, M., & Paccagnella, A. (2012). High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems https://doi.org/10.1109/DFT.2012.6378211

@inproceedings{49438e3b90cd4139859428e84f62523a,

title = "High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies",

abstract = "This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section.",

author = "C. Bolchini and A. Miele and C. Sandionigi and M. Ottavi and S. Pontarelli and A. Salsano and C. Metra and M. Oma{\~n}a and D. Rossi and M.S. Reorda and L. Sterpone and M. Violante and S. Gerardin and M. Bagatin and A. Paccagnella",

year = "2012",

doi = "10.1109/DFT.2012.6378211",

language = "English",

isbn = "978-1-4673-3043-5",

booktitle = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

note = "2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, DFT ; Conference date: 03-10-2012 Through 05-10-2012",

}

Bolchini, C, Miele, A, Sandionigi, C, Ottavi, M, Pontarelli, S, Salsano, A, Metra, C, Omaña, M, Rossi, D, Reorda, MS, Sterpone, L, Violante, M, Gerardin, S, Bagatin, M & Paccagnella, A 2012, High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, Texas, United States, 3/10/12. https://doi.org/10.1109/DFT.2012.6378211

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. / Bolchini, C.; Miele, A.; Sandionigi, C. et al.
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2012.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

AU - Bolchini, C.

AU - Miele, A.

AU - Sandionigi, C.

AU - Ottavi, M.

AU - Pontarelli, S.

AU - Salsano, A.

AU - Metra, C.

AU - Omaña, M.

AU - Rossi, D.

AU - Reorda, M.S.

AU - Sterpone, L.

AU - Violante, M.

AU - Gerardin, S.

AU - Bagatin, M.

AU - Paccagnella, A.

PY - 2012

Y1 - 2012

N2 - This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section.

AB - This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section.

UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84872297282&partnerID=MN8TOARS

U2 - 10.1109/DFT.2012.6378211

DO - 10.1109/DFT.2012.6378211

M3 - Conference contribution

SN - 978-1-4673-3043-5

BT - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

T2 - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012

Y2 - 3 October 2012 through 5 October 2012

ER -

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this