High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

C. Bolchini, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omaña, D. Rossi, M.S. Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Abstract

This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section.
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISBN (Electronic)978-1-4673-3044-2
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 - Austin, United States
Duration: 3 Oct 20125 Oct 2012

Conference

Conference2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
Abbreviated titleDFT
Country/TerritoryUnited States
CityAustin
Period3/10/125/10/12

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