High-speed low-jitter frequency multiplication in CMOS

Remco Cornelis Herman van de Beek

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    42 Downloads (Pure)

    Abstract

    This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speed¿ applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback mechanism that synchronizes the generated signal to the reference.
    Original languageEnglish
    Award date8 Jan 2004
    Place of PublicationEnschede
    Publisher
    Print ISBNs9789036519892
    Publication statusPublished - 2004

    Keywords

    • IR-41485

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