This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speed¿ applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback mechanism that synchronizes the generated signal to the reference.
|Award date||8 Jan 2004|
|Place of Publication||Enschede|
|Publication status||Published - 2004|