High-speed low-jitter frequency multiplication in CMOS

Remco Cornelis Herman van de Beek

High-speed low-jitter frequency multiplication in CMOS

Remco Cornelis Herman van de Beek

Research output: Thesis › PhD Thesis - Research UT, graduation UT

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Abstract

This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speed¿ applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback mechanism that synchronizes the generated signal to the reference.

Original language	English
Award date	8 Jan 2004
Place of Publication	Enschede
Publisher	University of Twente
Print ISBNs	9789036519892
Publication status	Published - 2004

Keywords

IR-41485

Access to Document

thesis_van_de_BeekFinal published version, 4.03 MB

Cite this

@phdthesis{53c5b8e1957e45dba5b698a0c227b6ab,

title = "High-speed low-jitter frequency multiplication in CMOS",

abstract = "This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speed¿ applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback mechanism that synchronizes the generated signal to the reference.",

keywords = "IR-41485",

author = "{van de Beek}, {Remco Cornelis Herman}",

year = "2004",

language = "English",

isbn = "9789036519892",

publisher = "University of Twente",

address = "Netherlands",

}

TY - THES

T1 - High-speed low-jitter frequency multiplication in CMOS

AU - van de Beek, Remco Cornelis Herman

PY - 2004

Y1 - 2004

N2 - This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speed¿ applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback mechanism that synchronizes the generated signal to the reference.

AB - This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speed¿ applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback mechanism that synchronizes the generated signal to the reference.

KW - IR-41485

M3 - PhD Thesis - Research UT, graduation UT

SN - 9789036519892

PB - University of Twente

CY - Enschede

ER -