High speed VLSI neural network for high energy physics

P. Masa, P. Masa, K. Hoen, Klaas Hoen, Hans Wallinga

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)
    76 Downloads (Pure)

    Abstract

    A CMOS neural network IC is discussed which was designed for very high speed applications. The parallel architecture, analog computing and digital weight storage provides unprecedented computing speed combined with ease of use. The circuit classifies up to 70 dimensional vectors within 20 nanoseconds, performing 20 billion (2*1010) multiply-and-add operations per second, and has as high as 28-42 Gbits/second equivalent input bandwidth with less than 1 W dissipation. The synaptic weights can be directly downloaded from a host computer to the on on-chip SRAM. The full-custom, analog-digital chip implements a fully connected feedforward neural network with 70 inputs, 6 hidden layer neurons and one output neuron. A unique solution, a single chip neural network photon trigger for high-energy physics research is provided
    Original languageEnglish
    Title of host publicationProceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, 1994
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE
    Pages422-428
    ISBN (Print)0-8186-6710-9
    DOIs
    Publication statusPublished - 24 Sep 1994
    Event4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994 - Turin, Italy
    Duration: 26 Sep 199428 Sep 1994
    Conference number: 4

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, ICMNN 1994
    Abbreviated titleICMNN
    CountryItaly
    CityTurin
    Period26/09/9428/09/94

    Keywords

    • IR-17089
    • METIS-113977

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