High throughput and low power dissipation in QCA pipelines using Bennett clocking

Marco Ottavi; S. Pontarelli; Erik DeBenedictis; Adelio Salsano; Peter Kogge; Fabrizio Lombarde

doi:10.1109/NANOARCH.2010.5510931

High throughput and low power dissipation in QCA pipelines using Bennett clocking

Marco Ottavi, S. Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter Kogge, Fabrizio Lombarde

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

Abstract

This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.

Original language	English
Title of host publication	2010 IEEE/ACM International Symposium on Nanoscale Architectures
ISBN (Electronic)	978-1-4244-8019-7
DOIs	https://doi.org/10.1109/NANOARCH.2010.5510931
Publication status	Published - 2010
Externally published	Yes
Event	IEEE/ACM International Symposium on Nanoscale Architectures 2010 - Anaheim, United States Duration: 17 Jun 2010 → 18 Jun 2010

Conference

Conference	IEEE/ACM International Symposium on Nanoscale Architectures 2010
Country/Territory	United States
City	Anaheim
Period	17/06/10 → 18/06/10

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10.1109/NANOARCH.2010.5510931

Cite this

@inproceedings{b27d21d80f4649d796f6c059d9d350ed,

title = "High throughput and low power dissipation in QCA pipelines using Bennett clocking",

abstract = "This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.",

author = "Marco Ottavi and S. Pontarelli and Erik DeBenedictis and Adelio Salsano and Peter Kogge and Fabrizio Lombarde",

year = "2010",

doi = "10.1109/NANOARCH.2010.5510931",

language = "English",

isbn = "978-1-4244-8020-3",

booktitle = "2010 IEEE/ACM International Symposium on Nanoscale Architectures",

note = "IEEE/ACM International Symposium on Nanoscale Architectures 2010 ; Conference date: 17-06-2010 Through 18-06-2010",

}

Ottavi, M, Pontarelli, S, DeBenedictis, E, Salsano, A, Kogge, P & Lombarde, F 2010, High throughput and low power dissipation in QCA pipelines using Bennett clocking. in 2010 IEEE/ACM International Symposium on Nanoscale Architectures. IEEE/ACM International Symposium on Nanoscale Architectures 2010, Anaheim, California, United States, 17/06/10. https://doi.org/10.1109/NANOARCH.2010.5510931

TY - GEN

T1 - High throughput and low power dissipation in QCA pipelines using Bennett clocking

AU - Ottavi, Marco

AU - Pontarelli, S.

AU - DeBenedictis, Erik

AU - Salsano, Adelio

AU - Kogge, Peter

AU - Lombarde, Fabrizio

PY - 2010

Y1 - 2010

N2 - This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.

AB - This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.

U2 - 10.1109/NANOARCH.2010.5510931

DO - 10.1109/NANOARCH.2010.5510931

M3 - Conference contribution

SN - 978-1-4244-8020-3

BT - 2010 IEEE/ACM International Symposium on Nanoscale Architectures

T2 - IEEE/ACM International Symposium on Nanoscale Architectures 2010

Y2 - 17 June 2010 through 18 June 2010

ER -

High throughput and low power dissipation in QCA pipelines using Bennett clocking

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