TY - JOUR
T1 - High voltage implanted RESURF p-LDMOS using BiCMOS technology
AU - Zhou, Ming-Jiang
AU - De Bruycker, A.
AU - Van Calster, A.
AU - Witters, J.
PY - 1993
Y1 - 1993
N2 - Summary form only given. The authors present a complementary RESURF p-LDMOS in which the n+ buried layer is used as an effective substrate and a field implant is introduced to modify the drift charges. The implant conditions in this case, particularly the placements, are studied. After processing, VB are investigated with different implant placement (LA, LB) and field oxide lengths LF. It is found that although the ion implant covers part of the drift region, the device performance can still be greatly improved. Results show that a long enough implant, compatible with LF, under the field oxide can result in the maximum, VB= VBP. This is verified by simulation results, which show that the peak of the surface electric field is significantly reduced. Results also show that a full length (LF) implantation under the field oxide can result in the minimum R on for a fixed LF
AB - Summary form only given. The authors present a complementary RESURF p-LDMOS in which the n+ buried layer is used as an effective substrate and a field implant is introduced to modify the drift charges. The implant conditions in this case, particularly the placements, are studied. After processing, VB are investigated with different implant placement (LA, LB) and field oxide lengths LF. It is found that although the ion implant covers part of the drift region, the device performance can still be greatly improved. Results show that a long enough implant, compatible with LF, under the field oxide can result in the maximum, VB= VBP. This is verified by simulation results, which show that the peak of the surface electric field is significantly reduced. Results also show that a full length (LF) implantation under the field oxide can result in the minimum R on for a fixed LF
U2 - 10.1109/16.239814
DO - 10.1109/16.239814
M3 - Article
SN - 0018-9383
VL - 40
SP - 425
EP - 429
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 11
ER -