Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors

This paper describes the usage of IDDX monitors, which provide (periodic) data to be employed for predicting the remaining lifetime of processor cores in homogeneous multi-processor SoCs during their lifetime. This forms the basis of self-repair with no mean down time for these SoCs and dramatically improving their dependability. We accomplish this goal by optimally choosing and combining our designed health monitors, such as delay and current monitors to provide non-redundant measurement data. These can be implemented nowadays as IJATG-compatible embedded instruments. Accelerated stress tests were carried out using a set of processor cores in combination with a number of health monitors providing historic data. These results form the basis of a remaining lifetime prediction model for delay (processor clock frequency), where the coefficients are determined by a genetic algorithm. After the final test of an individual SoC, these stored coefficients can be periodically updated in an embedded processor during its lifetime by the health monitors. In the case of seriously degrading cores, counteractions are automatically taken, like core isolation and (e.g. spare) replacement. In this case, use is made of advanced run-time mapping software. The result is a zero mean downtime SoC with 40% reliability improvement in our 9 processor-core SoC.