Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors

Yong Zhao (Editor), Hans G. Kerkhoff

Research output: Contribution to conferencePaperAcademicpeer-review

5 Citations (Scopus)
4 Downloads (Pure)

Abstract

This paper describes the usage of IDDX monitors, which provide (periodic) data to be employed for predicting the remaining lifetime of processor cores in homogeneous multi-processor SoCs during their lifetime. This forms the basis of self-repair with no mean down time for these SoCs and dramatically improving their dependability. We accomplish this goal by optimally choosing and combining our designed health monitors, such as delay and current monitors to provide non-redundant measurement data. These can be implemented nowadays as IJATG-compatible embedded instruments. Accelerated stress tests were carried out using a set of processor cores in combination with a number of health monitors providing historic data. These results form the basis of a remaining lifetime prediction model for delay (processor clock frequency), where the coefficients are determined by a genetic algorithm. After the final test of an individual SoC, these stored coefficients can be periodically updated in an embedded processor during its lifetime by the health monitors. In the case of seriously degrading cores, counteractions are automatically taken, like core isolation and (e.g. spare) replacement. In this case, use is made of advanced run-time mapping software. The result is a zero mean downtime SoC with 40% reliability improvement in our 9 processor-core SoC.
Original languageUndefined
Pages228-233
Number of pages6
DOIs
Publication statusPublished - Nov 2016

Keywords

  • IR-104412
  • health monitors
  • dependable MP-SoC
  • delay testing
  • iJTAG embedded instruments
  • EC Grant Agreement nr.: FP7/619871
  • EC Grant Agreement nr.: FP7/644905
  • TC
  • EWI-26192
  • HTOL
  • IDDX testing
  • lifetime prediction

Cite this

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title = "Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors",
abstract = "This paper describes the usage of IDDX monitors, which provide (periodic) data to be employed for predicting the remaining lifetime of processor cores in homogeneous multi-processor SoCs during their lifetime. This forms the basis of self-repair with no mean down time for these SoCs and dramatically improving their dependability. We accomplish this goal by optimally choosing and combining our designed health monitors, such as delay and current monitors to provide non-redundant measurement data. These can be implemented nowadays as IJATG-compatible embedded instruments. Accelerated stress tests were carried out using a set of processor cores in combination with a number of health monitors providing historic data. These results form the basis of a remaining lifetime prediction model for delay (processor clock frequency), where the coefficients are determined by a genetic algorithm. After the final test of an individual SoC, these stored coefficients can be periodically updated in an embedded processor during its lifetime by the health monitors. In the case of seriously degrading cores, counteractions are automatically taken, like core isolation and (e.g. spare) replacement. In this case, use is made of advanced run-time mapping software. The result is a zero mean downtime SoC with 40{\%} reliability improvement in our 9 processor-core SoC.",
keywords = "IR-104412, health monitors, dependable MP-SoC, delay testing, iJTAG embedded instruments, EC Grant Agreement nr.: FP7/619871, EC Grant Agreement nr.: FP7/644905, TC, EWI-26192, HTOL, IDDX testing, lifetime prediction",
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Highly dependable multi-processor SoCs employing lifetime prediction based on health monitors. / Zhao, Yong (Editor); Kerkhoff, Hans G.

2016. 228-233.

Research output: Contribution to conferencePaperAcademicpeer-review

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AB - This paper describes the usage of IDDX monitors, which provide (periodic) data to be employed for predicting the remaining lifetime of processor cores in homogeneous multi-processor SoCs during their lifetime. This forms the basis of self-repair with no mean down time for these SoCs and dramatically improving their dependability. We accomplish this goal by optimally choosing and combining our designed health monitors, such as delay and current monitors to provide non-redundant measurement data. These can be implemented nowadays as IJATG-compatible embedded instruments. Accelerated stress tests were carried out using a set of processor cores in combination with a number of health monitors providing historic data. These results form the basis of a remaining lifetime prediction model for delay (processor clock frequency), where the coefficients are determined by a genetic algorithm. After the final test of an individual SoC, these stored coefficients can be periodically updated in an embedded processor during its lifetime by the health monitors. In the case of seriously degrading cores, counteractions are automatically taken, like core isolation and (e.g. spare) replacement. In this case, use is made of advanced run-time mapping software. The result is a zero mean downtime SoC with 40% reliability improvement in our 9 processor-core SoC.

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